{"id":"https://openalex.org/W2087362496","doi":"https://doi.org/10.1109/eurocon.2011.5929348","title":"VHDL structural model visualization","display_name":"VHDL structural model visualization","publication_year":2011,"publication_date":"2011-04-01","ids":{"openalex":"https://openalex.org/W2087362496","doi":"https://doi.org/10.1109/eurocon.2011.5929348","mag":"2087362496"},"language":"en","primary_location":{"id":"doi:10.1109/eurocon.2011.5929348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eurocon.2011.5929348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE EUROCON - International Conference on Computer as a Tool","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079722422","display_name":"Dominik Macko","orcid":"https://orcid.org/0000-0002-8235-2004"},"institutions":[{"id":"https://openalex.org/I110757952","display_name":"Slovak University of Technology in Bratislava","ror":"https://ror.org/0561ghm58","country_code":"SK","type":"education","lineage":["https://openalex.org/I110757952"]}],"countries":["SK"],"is_corresponding":false,"raw_author_name":"D. Macko","raw_affiliation_strings":["Faculty of Informatics and Information Technologies, Slovak University of Technology, Bratislava, Slovakia","Slovak University of Technology, Faculty of Informatics and Information Technologies, Bratislava, Slovakia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Informatics and Information Technologies, Slovak University of Technology, Bratislava, Slovakia","institution_ids":["https://openalex.org/I110757952"]},{"raw_affiliation_string":"Slovak University of Technology, Faculty of Informatics and Information Technologies, Bratislava, Slovakia","institution_ids":["https://openalex.org/I110757952"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5012166109","display_name":"Katar\u00edna Jelemensk\u00e1","orcid":null},"institutions":[{"id":"https://openalex.org/I110757952","display_name":"Slovak University of Technology in Bratislava","ror":"https://ror.org/0561ghm58","country_code":"SK","type":"education","lineage":["https://openalex.org/I110757952"]}],"countries":["SK"],"is_corresponding":false,"raw_author_name":"K. Jelemenska","raw_affiliation_strings":["Faculty of Informatics and Information Technologies, Slovak University of Technology, Bratislava, Slovakia","Slovak University of Technology, Faculty of Informatics and Information Technologies, Bratislava, Slovakia"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Faculty of Informatics and Information Technologies, Slovak University of Technology, Bratislava, Slovakia","institution_ids":["https://openalex.org/I110757952"]},{"raw_affiliation_string":"Slovak University of Technology, Faculty of Informatics and Information Technologies, Bratislava, Slovakia","institution_ids":["https://openalex.org/I110757952"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I110757952"],"apc_list":null,"apc_paid":null,"fwci":1.7468,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.82797065,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12810","display_name":"Real-time simulation and control systems","score":0.9876999855041504,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9625999927520752,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.954800009727478,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8337399363517761},{"id":"https://openalex.org/keywords/visualization","display_name":"Visualization","score":0.7996259927749634},{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.7546532154083252},{"id":"https://openalex.org/keywords/debugging","display_name":"Debugging","score":0.7350248694419861},{"id":"https://openalex.org/keywords/schematic","display_name":"Schematic","score":0.7187417149543762},{"id":"https://openalex.org/keywords/hardware-description-language","display_name":"Hardware description language","score":0.550853967666626},{"id":"https://openalex.org/keywords/electronic-design-automation","display_name":"Electronic design automation","score":0.5010533332824707},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46891674399375916},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.46796804666519165},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.4084608554840088},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.40381479263305664},{"id":"https://openalex.org/keywords/engineering-drawing","display_name":"Engineering drawing","score":0.37518298625946045},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.26668035984039307},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.2164207398891449},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.16762027144432068},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.0885363519191742}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8337399363517761},{"id":"https://openalex.org/C36464697","wikidata":"https://www.wikidata.org/wiki/Q451553","display_name":"Visualization","level":2,"score":0.7996259927749634},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.7546532154083252},{"id":"https://openalex.org/C168065819","wikidata":"https://www.wikidata.org/wiki/Q845566","display_name":"Debugging","level":2,"score":0.7350248694419861},{"id":"https://openalex.org/C192328126","wikidata":"https://www.wikidata.org/wiki/Q4514647","display_name":"Schematic","level":2,"score":0.7187417149543762},{"id":"https://openalex.org/C42143788","wikidata":"https://www.wikidata.org/wiki/Q173341","display_name":"Hardware description language","level":3,"score":0.550853967666626},{"id":"https://openalex.org/C64260653","wikidata":"https://www.wikidata.org/wiki/Q1194864","display_name":"Electronic design automation","level":2,"score":0.5010533332824707},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46891674399375916},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.46796804666519165},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.4084608554840088},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.40381479263305664},{"id":"https://openalex.org/C199639397","wikidata":"https://www.wikidata.org/wiki/Q1788588","display_name":"Engineering drawing","level":1,"score":0.37518298625946045},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.26668035984039307},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.2164207398891449},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.16762027144432068},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.0885363519191742},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.0},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eurocon.2011.5929348","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eurocon.2011.5929348","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 IEEE EUROCON - International Conference on Computer as a Tool","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Quality Education","id":"https://metadata.un.org/sdg/4","score":0.800000011920929}],"awards":[],"funders":[{"id":"https://openalex.org/F4320330700","display_name":"Slovensk\u00e1 technick\u00e1 univerzita v Bratislave","ror":"https://ror.org/0561ghm58"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W1891842933","https://openalex.org/W2129602408","https://openalex.org/W2163427621"],"related_works":["https://openalex.org/W2110818533","https://openalex.org/W1917852300","https://openalex.org/W2139058049","https://openalex.org/W2376018793","https://openalex.org/W2548456620","https://openalex.org/W2911649771","https://openalex.org/W2148697719","https://openalex.org/W2384838054","https://openalex.org/W2370873755","https://openalex.org/W2389698729"],"abstract_inverted_index":{"Nowadays":[0],"the":[1,16,23,36,39,55,98,118,121,129,134,139,148,152,157,162,177,186,195,198],"digital":[2],"systems":[3,71,90],"design":[4,37,130],"is":[5,22,61],"almost":[6],"exclusively":[7],"realized":[8],"using":[9],"hardware":[10],"description":[11],"languages":[12],"(HDL).":[13],"In":[14,101],"Europe,":[15],"VHDL":[17,140,159,199],"(Very-High-Speed":[18],"Integrated":[19],"Circuits":[20],"HDL)":[21],"most":[24],"widely":[25],"used":[26,57],"HDL.":[27],"Although":[28],"HDLs":[29],"brought":[30],"a":[31,63,81,85],"lot":[32,64],"of":[33,65,75,120,133,197],"advantages":[34],"into":[35],"process,":[38],"HDL":[40],"structural":[41,122,141,200],"models,":[42],"especially":[43],"on":[44],"register":[45],"transfer":[46],"and":[47,95,131,180,203],"lower":[48],"layers,":[49],"are":[50,91],"harder":[51],"to":[52,79,106,138,150,156,170,182],"read":[53],"than":[54],"previously":[56],"schematic":[58,153,163],"representations.":[59],"That":[60],"why":[62],"commercial":[66],"EDA":[67],"(Electronic":[68],"Design":[69],"Automation)":[70],"include":[72],"some":[73],"kind":[74],"visualization":[76,108,124,135],"tool":[77,109,136,146,175,193],"enabling":[78],"represent":[80],"model":[82,178,201],"structure":[83],"in":[84,194],"graphical":[86],"form.":[87],"However,":[88],"these":[89],"usually":[92],"too":[93],"complex":[94],"expensive":[96],"for":[97,208],"education":[99],"purpose.":[100],"this":[102],"case":[103],"simple,":[104],"easy":[105],"use":[107],"would":[110],"be":[111],"more":[112],"appropriate.":[113],"The":[114,144,174],"paper":[115],"deals":[116],"with":[117,128],"problem":[119],"models":[123,142],"as":[125,127,205,207],"well":[126,206],"implementation":[132],"devoted":[137],"visualization.":[143],"presented":[145],"offers":[147],"possibility":[149],"display":[151],"view":[154],"corresponding":[155],"input":[158],"model,":[160],"edit":[161],"layout,":[164],"print":[165],"it":[166,169],"or":[167],"export":[168],"an":[171,191],"image":[172],"file.":[173],"preserves":[176],"hierarchy":[179],"enables":[181],"easily":[183],"switch":[184],"among":[185],"respective":[187],"levels.":[188],"It":[189],"represents":[190],"useful":[192],"process":[196],"verification":[202],"debugging":[204],"documentation":[209],"purposes.":[210]},"counts_by_year":[{"year":2013,"cited_by_count":2},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}