{"id":"https://openalex.org/W2143354328","doi":"https://doi.org/10.1109/etw.2002.1029638","title":"Novel ATPG algorithms for transition faults","display_name":"Novel ATPG algorithms for transition faults","publication_year":2003,"publication_date":"2003-06-25","ids":{"openalex":"https://openalex.org/W2143354328","doi":"https://doi.org/10.1109/etw.2002.1029638","mag":"2143354328"},"language":"en","primary_location":{"id":"doi:10.1109/etw.2002.1029638","is_oa":false,"landing_page_url":"https://doi.org/10.1109/etw.2002.1029638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings The Seventh IEEE European Test Workshop","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075936732","display_name":"Xiao Liu","orcid":"https://orcid.org/0000-0001-8400-5754"},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Xiao Liu","raw_affiliation_strings":["The Bradley Department Electrical & Computer Engineering, Virginia Polytechnic Institute and State University, USA","Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Bradley Department Electrical & Computer Engineering, Virginia Polytechnic Institute and State University, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108516165","display_name":"Michael S. Hsiao","orcid":null},"institutions":[{"id":"https://openalex.org/I859038795","display_name":"Virginia Tech","ror":"https://ror.org/02smfhw86","country_code":"US","type":"education","lineage":["https://openalex.org/I859038795"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"M.S. Hsiao","raw_affiliation_strings":["The Bradley Department Electrical & Computer Engineering, Virginia Polytechnic Institute and State University, USA","Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"The Bradley Department Electrical & Computer Engineering, Virginia Polytechnic Institute and State University, USA","institution_ids":["https://openalex.org/I859038795"]},{"raw_affiliation_string":"Bradley Dept. of Electr. Eng., Virginia Polytech. Inst. & State Univ., Blacksburg, VA, USA","institution_ids":["https://openalex.org/I859038795"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5087206490","display_name":"S. Chakravarty","orcid":"https://orcid.org/0000-0002-3682-2060"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"S. Chakravarty","raw_affiliation_strings":["Intel Architecture Group, Intel Corporation, USA","Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Architecture Group, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043215850","display_name":"Paul J. Thadikaran","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I4210158342","display_name":"Intel (United Kingdom)","ror":"https://ror.org/058cxws58","country_code":"GB","type":"company","lineage":["https://openalex.org/I1343180700","https://openalex.org/I4210158342"]}],"countries":["GB","US"],"is_corresponding":false,"raw_author_name":"P.J. Thadikaran","raw_affiliation_strings":["Intel Architecture Group, Intel Corporation, USA","Intel Corporation"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Architecture Group, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corporation","institution_ids":["https://openalex.org/I4210158342"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":18,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"47","last_page":"52"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9966999888420105,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.9282596111297607},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.7376067638397217},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6210533380508423},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.5723773241043091},{"id":"https://openalex.org/keywords/combinational-logic","display_name":"Combinational logic","score":0.5653568506240845},{"id":"https://openalex.org/keywords/test-compression","display_name":"Test compression","score":0.5541545152664185},{"id":"https://openalex.org/keywords/test-set","display_name":"Test set","score":0.5284165143966675},{"id":"https://openalex.org/keywords/constraint","display_name":"Constraint (computer-aided design)","score":0.47593072056770325},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.451330304145813},{"id":"https://openalex.org/keywords/construct","display_name":"Construct (python library)","score":0.43322306871414185},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.4270641803741455},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.35355111956596375},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.2937007546424866},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1936018168926239},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.17271077632904053},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.15744492411613464},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.15691065788269043},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.06473240256309509}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.9282596111297607},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.7376067638397217},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6210533380508423},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.5723773241043091},{"id":"https://openalex.org/C81409106","wikidata":"https://www.wikidata.org/wiki/Q76505","display_name":"Combinational logic","level":3,"score":0.5653568506240845},{"id":"https://openalex.org/C29652920","wikidata":"https://www.wikidata.org/wiki/Q7705757","display_name":"Test compression","level":4,"score":0.5541545152664185},{"id":"https://openalex.org/C169903167","wikidata":"https://www.wikidata.org/wiki/Q3985153","display_name":"Test set","level":2,"score":0.5284165143966675},{"id":"https://openalex.org/C2776036281","wikidata":"https://www.wikidata.org/wiki/Q48769818","display_name":"Constraint (computer-aided design)","level":2,"score":0.47593072056770325},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.451330304145813},{"id":"https://openalex.org/C2780801425","wikidata":"https://www.wikidata.org/wiki/Q5164392","display_name":"Construct (python library)","level":2,"score":0.43322306871414185},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.4270641803741455},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.35355111956596375},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.2937007546424866},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1936018168926239},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.17271077632904053},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.15744492411613464},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.15691065788269043},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.06473240256309509},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C78519656","wikidata":"https://www.wikidata.org/wiki/Q101333","display_name":"Mechanical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/etw.2002.1029638","is_oa":false,"landing_page_url":"https://doi.org/10.1109/etw.2002.1029638","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings The Seventh IEEE European Test Workshop","raw_type":"proceedings-article"},{"id":"pmh:oai:CiteSeerX.psu:10.1.1.122.6558","is_oa":false,"landing_page_url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.122.6558","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"http://csdl.computer.org/comp/proceedings/etw/2002/1715/00/17150047.pdf","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6299999952316284,"display_name":"Decent work and economic growth","id":"https://metadata.un.org/sdg/8"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W13277579","https://openalex.org/W1859798932","https://openalex.org/W1969474413","https://openalex.org/W2061946964","https://openalex.org/W2096110076","https://openalex.org/W2108103162","https://openalex.org/W2110164501","https://openalex.org/W2118744758","https://openalex.org/W2143744297","https://openalex.org/W2160010735","https://openalex.org/W2165817266","https://openalex.org/W2168755502","https://openalex.org/W3149357776","https://openalex.org/W3149518392","https://openalex.org/W6600530048"],"related_works":["https://openalex.org/W2786111245","https://openalex.org/W3009953521","https://openalex.org/W4285708951","https://openalex.org/W1991935474","https://openalex.org/W2021253405","https://openalex.org/W2091533492","https://openalex.org/W2323083271","https://openalex.org/W2802691720","https://openalex.org/W2940545572","https://openalex.org/W2543176856"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"novel":[3],"algorithms":[4,21,42,51],"for":[5,9],"computing":[6],"test":[7,39,60,63,67,76],"patterns":[8],"transition":[10,38,75],"faults":[11],"in":[12,59,82],"combinational":[13],"circuits":[14],"and":[15,66,95],"fully":[16],"scanned":[17],"sequential":[18],"circuits.":[19],"The":[20],"are":[22,43,99],"based":[23],"on":[24],"the":[25,49],"principle":[26],"that":[27,53],"s@":[28],"vectors":[29],"can":[30],"be":[31],"effectively":[32],"used":[33],"to":[34,71],"construct":[35],"good":[36],"quality":[37],"sets.":[40],"Several":[41],"discussed.":[44],"Experimental":[45],"results":[46],"obtained":[47],"using":[48],"new":[50],"show":[52],"there":[54],"is":[55],"a":[56,72],"20%":[57],"reduction":[58,81],"set":[61],"size,":[62],"data":[64,97],"volume":[65],"application":[68],"time":[69],"compared":[70],"state-of-the-art":[73],"native":[74],"ATPG":[77],"tool,":[78],"without":[79],"any":[80],"fault":[83],"coverage.":[84],"Other":[85],"benefits":[86],"of":[87],"our":[88],"approach,":[89],"viz.":[90],"productivity":[91],"improvement,":[92],"constraint":[93],"handling":[94],"design":[96],"compression":[98],"highlighted.":[100]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}