{"id":"https://openalex.org/W2147248543","doi":"https://doi.org/10.1109/etsym.2004.1347655","title":"A design methodology to realize delay testable controllers using state transition information","display_name":"A design methodology to realize delay testable controllers using state transition information","publication_year":2004,"publication_date":"2004-11-08","ids":{"openalex":"https://openalex.org/W2147248543","doi":"https://doi.org/10.1109/etsym.2004.1347655","mag":"2147248543"},"language":"en","primary_location":{"id":"doi:10.1109/etsym.2004.1347655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/etsym.2004.1347655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5076872212","display_name":"Tsuyoshi Iwagaki","orcid":null},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"T. Iwagaki","raw_affiliation_strings":["Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan",", Nara Institute of Science and Technology"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan","institution_ids":["https://openalex.org/I75917431"]},{"raw_affiliation_string":", Nara Institute of Science and Technology","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5022717526","display_name":"Satoshi Ohtake","orcid":null},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"S. Ohtake","raw_affiliation_strings":["Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan","Nara Institute of Science and Technology , Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan","institution_ids":["https://openalex.org/I75917431"]},{"raw_affiliation_string":"Nara Institute of Science and Technology , Japan","institution_ids":["https://openalex.org/I75917431"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111955990","display_name":"Hideo Fujiwara","orcid":null},"institutions":[{"id":"https://openalex.org/I75917431","display_name":"Nara Institute of Science and Technology","ror":"https://ror.org/05bhada84","country_code":"JP","type":"education","lineage":["https://openalex.org/I75917431"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"H. Fujiwara","raw_affiliation_strings":["Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan","Nara Institute of Science and Technology , Japan"],"affiliations":[{"raw_affiliation_string":"Graduate School of Information Science, Nara Institute of Science and Technology, Kansai Science, Japan","institution_ids":["https://openalex.org/I75917431"]},{"raw_affiliation_string":"Nara Institute of Science and Technology , Japan","institution_ids":["https://openalex.org/I75917431"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5076872212"],"corresponding_institution_ids":["https://openalex.org/I75917431"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.17238679,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"168","last_page":"173"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.9894000291824341,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.7183196544647217},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6674516797065735},{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.6609194874763489},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.6334766745567322},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5739004611968994},{"id":"https://openalex.org/keywords/state","display_name":"State (computer science)","score":0.5518152713775635},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.49328774213790894},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.48629435896873474},{"id":"https://openalex.org/keywords/sequential-logic","display_name":"Sequential logic","score":0.45595434308052063},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4465569257736206},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.44599488377571106},{"id":"https://openalex.org/keywords/graph","display_name":"Graph","score":0.41800469160079956},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.39678195118904114},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.3201104402542114},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.28161701560020447},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.2336713671684265},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22507831454277039},{"id":"https://openalex.org/keywords/control","display_name":"Control (management)","score":0.19161555171012878},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.13797718286514282},{"id":"https://openalex.org/keywords/theoretical-computer-science","display_name":"Theoretical computer science","score":0.111208975315094},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10418865084648132}],"concepts":[{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.7183196544647217},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6674516797065735},{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.6609194874763489},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.6334766745567322},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5739004611968994},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.5518152713775635},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.49328774213790894},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.48629435896873474},{"id":"https://openalex.org/C187075797","wikidata":"https://www.wikidata.org/wiki/Q173245","display_name":"Sequential logic","level":3,"score":0.45595434308052063},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4465569257736206},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.44599488377571106},{"id":"https://openalex.org/C132525143","wikidata":"https://www.wikidata.org/wiki/Q141488","display_name":"Graph","level":2,"score":0.41800469160079956},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.39678195118904114},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.3201104402542114},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.28161701560020447},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.2336713671684265},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22507831454277039},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.19161555171012878},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.13797718286514282},{"id":"https://openalex.org/C80444323","wikidata":"https://www.wikidata.org/wiki/Q2878974","display_name":"Theoretical computer science","level":1,"score":0.111208975315094},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10418865084648132},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C165205528","wikidata":"https://www.wikidata.org/wiki/Q83371","display_name":"Seismology","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.0},{"id":"https://openalex.org/C127313418","wikidata":"https://www.wikidata.org/wiki/Q1069","display_name":"Geology","level":0,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/etsym.2004.1347655","is_oa":false,"landing_page_url":"https://doi.org/10.1109/etsym.2004.1347655","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":13,"referenced_works":["https://openalex.org/W124614662","https://openalex.org/W204937362","https://openalex.org/W1568407911","https://openalex.org/W1704440991","https://openalex.org/W1963503916","https://openalex.org/W2096146619","https://openalex.org/W2108103162","https://openalex.org/W2110164501","https://openalex.org/W2117240012","https://openalex.org/W2118744758","https://openalex.org/W2133913685","https://openalex.org/W2148870521","https://openalex.org/W2497118556"],"related_works":["https://openalex.org/W2369589212","https://openalex.org/W2543176856","https://openalex.org/W1579528621","https://openalex.org/W2117873690","https://openalex.org/W2141620082","https://openalex.org/W3141249762","https://openalex.org/W2137555930","https://openalex.org/W2168652618","https://openalex.org/W2157154381","https://openalex.org/W4253743993"],"abstract_inverted_index":{"This":[0],"paper":[1],"proposes":[2],"a":[3,19],"non-scan":[4],"design":[5,56],"scheme":[6,74],"to":[7,25,68],"enhance":[8],"delay":[9,27],"fault":[10],"testability":[11],"of":[12,36,88],"controllers.":[13],"In":[14],"this":[15],"scheme,":[16],"we":[17,55],"utilize":[18],"given":[20],"state":[21,64],"transition":[22,66],"graph":[23],"(STG)":[24],"test":[26,42,63,78],"faults":[28,45,71],"in":[29],"its":[30],"synthesized":[31],"controller.":[32],"The":[33],"original":[34,53],"behavior":[35],"the":[37,52,86],"STG":[38],"is":[39],"used":[40],"during":[41],"application.":[43],"For":[44],"that":[46],"cannot":[47],"be":[48],"detected":[49],"by":[50,91],"using":[51],"behavior,":[54],"an":[57,61],"extra":[58],"logic,":[59],"called":[60],"invalid":[62],"and":[65,81],"generator,":[67],"make":[69],"those":[70],"detectable.":[72],"Our":[73],"allows":[75],"achieving":[76],"short":[77],"application":[79],"time":[80],"at-speed":[82],"testing.":[83],"We":[84],"show":[85],"effectiveness":[87],"our":[89],"method":[90],"experiments.":[92]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
