{"id":"https://openalex.org/W7167923366","doi":"https://doi.org/10.1109/ets69887.2026.11591982","title":"Fault Model-Driven Formal Verification of Cryptographic Hardware Against Fault Attacks","display_name":"Fault Model-Driven Formal Verification of Cryptographic Hardware Against Fault Attacks","publication_year":2026,"publication_date":"2026-05-25","ids":{"openalex":"https://openalex.org/W7167923366","doi":"https://doi.org/10.1109/ets69887.2026.11591982"},"language":null,"primary_location":{"id":"doi:10.1109/ets69887.2026.11591982","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets69887.2026.11591982","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5117630339","display_name":"Daniel Thirion","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]},{"id":"https://openalex.org/I4210135508","display_name":"STMicroelectronics (United Kingdom)","ror":"https://ror.org/0442wxc77","country_code":"GB","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210135508"]}],"countries":["GB","IN"],"is_corresponding":false,"raw_author_name":"Daniel Thirion","raw_affiliation_strings":["850 Rue Jean Monnet,STMicroelectronics,Crolles Cedex,France,38926"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"850 Rue Jean Monnet,STMicroelectronics,Crolles Cedex,France,38926","institution_ids":["https://openalex.org/I4210094169","https://openalex.org/I4210135508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5140419801","display_name":"George-Cristian Sercaianu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]},{"id":"https://openalex.org/I4210135508","display_name":"STMicroelectronics (United Kingdom)","ror":"https://ror.org/0442wxc77","country_code":"GB","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210135508"]}],"countries":["GB","IN"],"is_corresponding":false,"raw_author_name":"George-Cristian Sercaianu","raw_affiliation_strings":["850 Rue Jean Monnet,STMicroelectronics,Crolles Cedex,France,38926"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"850 Rue Jean Monnet,STMicroelectronics,Crolles Cedex,France,38926","institution_ids":["https://openalex.org/I4210094169","https://openalex.org/I4210135508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5046078698","display_name":"Valentin Egloff","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145979","display_name":"Laboratoire de Conception et d'Int\u00e9gration des Syst\u00e8mes","ror":"https://ror.org/04eg25g76","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I4210145979","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Valentin Egloff","raw_affiliation_strings":["Univ. Grenoble Alpes, Grenoble INP**, LCIS, 50 Rue Barthéémy de Laffemas,Valence,France,26000"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. Grenoble Alpes, Grenoble INP**, LCIS, 50 Rue Barthéémy de Laffemas,Valence,France,26000","institution_ids":["https://openalex.org/I4210145979","https://openalex.org/I899635006"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5140440662","display_name":"Jean-Marc Daveau","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]},{"id":"https://openalex.org/I4210135508","display_name":"STMicroelectronics (United Kingdom)","ror":"https://ror.org/0442wxc77","country_code":"GB","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210135508"]}],"countries":["GB","IN"],"is_corresponding":false,"raw_author_name":"Jean-Marc Daveau","raw_affiliation_strings":["850 Rue Jean Monnet,STMicroelectronics,Crolles Cedex,France,38926"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"850 Rue Jean Monnet,STMicroelectronics,Crolles Cedex,France,38926","institution_ids":["https://openalex.org/I4210094169","https://openalex.org/I4210135508"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5140437496","display_name":"Vincent Beroulle","orcid":null},"institutions":[{"id":"https://openalex.org/I4210145979","display_name":"Laboratoire de Conception et d'Int\u00e9gration des Syst\u00e8mes","ror":"https://ror.org/04eg25g76","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I4210145979","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Vincent Beroulle","raw_affiliation_strings":["Univ. Grenoble Alpes, Grenoble INP**, LCIS, 50 Rue Barthéémy de Laffemas,Valence,France,26000"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. Grenoble Alpes, Grenoble INP**, LCIS, 50 Rue Barthéémy de Laffemas,Valence,France,26000","institution_ids":["https://openalex.org/I4210145979","https://openalex.org/I899635006"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060495895","display_name":"David H\u00e9ly","orcid":"https://orcid.org/0000-0003-3249-7667"},"institutions":[{"id":"https://openalex.org/I4210145979","display_name":"Laboratoire de Conception et d'Int\u00e9gration des Syst\u00e8mes","ror":"https://ror.org/04eg25g76","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I4210145979","https://openalex.org/I899635006","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"David Hely","raw_affiliation_strings":["Univ. Grenoble Alpes, Grenoble INP**, LCIS, 50 Rue Barthéémy de Laffemas,Valence,France,26000"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Univ. Grenoble Alpes, Grenoble INP**, LCIS, 50 Rue Barthéémy de Laffemas,Valence,France,26000","institution_ids":["https://openalex.org/I4210145979","https://openalex.org/I899635006"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5140400912","display_name":"Philippe Roche","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]},{"id":"https://openalex.org/I4210135508","display_name":"STMicroelectronics (United Kingdom)","ror":"https://ror.org/0442wxc77","country_code":"GB","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210135508"]}],"countries":["GB","IN"],"is_corresponding":false,"raw_author_name":"Philippe Roche","raw_affiliation_strings":["850 Rue Jean Monnet,STMicroelectronics,Crolles Cedex,France,38926"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"850 Rue Jean Monnet,STMicroelectronics,Crolles Cedex,France,38926","institution_ids":["https://openalex.org/I4210094169","https://openalex.org/I4210135508"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.3402000069618225,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10142","display_name":"Formal Methods in Verification","score":0.3402000069618225,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.2524000108242035,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11424","display_name":"Security and Verification in Computing","score":0.1071000024676323,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cryptography","display_name":"Cryptography","score":0.4722000062465668},{"id":"https://openalex.org/keywords/fault","display_name":"Fault (geology)","score":0.47209998965263367},{"id":"https://openalex.org/keywords/formal-verification","display_name":"Formal verification","score":0.4106999933719635},{"id":"https://openalex.org/keywords/cryptographic-protocol","display_name":"Cryptographic protocol","score":0.3596999943256378},{"id":"https://openalex.org/keywords/formal-methods","display_name":"Formal methods","score":0.3531999886035919},{"id":"https://openalex.org/keywords/software","display_name":"Software","score":0.33329999446868896},{"id":"https://openalex.org/keywords/fault-injection","display_name":"Fault injection","score":0.3237999975681305}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.663100004196167},{"id":"https://openalex.org/C178489894","wikidata":"https://www.wikidata.org/wiki/Q8789","display_name":"Cryptography","level":2,"score":0.4722000062465668},{"id":"https://openalex.org/C175551986","wikidata":"https://www.wikidata.org/wiki/Q47089","display_name":"Fault (geology)","level":2,"score":0.47209998965263367},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4717999994754791},{"id":"https://openalex.org/C111498074","wikidata":"https://www.wikidata.org/wiki/Q173326","display_name":"Formal verification","level":2,"score":0.4106999933719635},{"id":"https://openalex.org/C33884865","wikidata":"https://www.wikidata.org/wiki/Q1254335","display_name":"Cryptographic protocol","level":3,"score":0.3596999943256378},{"id":"https://openalex.org/C75606506","wikidata":"https://www.wikidata.org/wiki/Q1049183","display_name":"Formal methods","level":2,"score":0.3531999886035919},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.33399999141693115},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.33329999446868896},{"id":"https://openalex.org/C2775928411","wikidata":"https://www.wikidata.org/wiki/Q2041312","display_name":"Fault injection","level":3,"score":0.3237999975681305},{"id":"https://openalex.org/C167391956","wikidata":"https://www.wikidata.org/wiki/Q1401211","display_name":"Fault model","level":3,"score":0.3100000023841858},{"id":"https://openalex.org/C95713431","wikidata":"https://www.wikidata.org/wiki/Q631425","display_name":"Vulnerability (computing)","level":2,"score":0.30820000171661377},{"id":"https://openalex.org/C96654402","wikidata":"https://www.wikidata.org/wiki/Q5469962","display_name":"Formal equivalence checking","level":3,"score":0.29170000553131104},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.28619998693466187},{"id":"https://openalex.org/C33054407","wikidata":"https://www.wikidata.org/wiki/Q6504747","display_name":"Software verification","level":5,"score":0.27320000529289246},{"id":"https://openalex.org/C48103436","wikidata":"https://www.wikidata.org/wiki/Q599031","display_name":"State (computer science)","level":2,"score":0.2728999853134155},{"id":"https://openalex.org/C15927051","wikidata":"https://www.wikidata.org/wiki/Q246593","display_name":"Cryptographic primitive","level":4,"score":0.2685999870300293},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.2678999900817871},{"id":"https://openalex.org/C116253237","wikidata":"https://www.wikidata.org/wiki/Q1437424","display_name":"Formal specification","level":2,"score":0.25189998745918274}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ets69887.2026.11591982","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets69887.2026.11591982","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2026 IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W347636100","https://openalex.org/W1537875328","https://openalex.org/W1573725807","https://openalex.org/W1599175145","https://openalex.org/W2037758572","https://openalex.org/W2085992264","https://openalex.org/W2107049974","https://openalex.org/W2110941647","https://openalex.org/W2111725598","https://openalex.org/W2170489924","https://openalex.org/W2280109954","https://openalex.org/W2346748018","https://openalex.org/W2602633208","https://openalex.org/W2954468923","https://openalex.org/W2989579477","https://openalex.org/W3008339931","https://openalex.org/W3133644504","https://openalex.org/W3149134903","https://openalex.org/W4248229502","https://openalex.org/W4386474821","https://openalex.org/W4402496328","https://openalex.org/W4410583589"],"related_works":[],"abstract_inverted_index":null,"counts_by_year":[],"updated_date":"2026-07-22T07:51:19.307946","created_date":"2026-07-11T00:00:00"}