{"id":"https://openalex.org/W7155367165","doi":"https://doi.org/10.1109/ets63895.2025.11049312","title":"A UCIe Compatible Repair Scheme for the Clustered Faults in the Hexagonal Array of Interconnect Lanes","display_name":"A UCIe Compatible Repair Scheme for the Clustered Faults in the Hexagonal Array of Interconnect Lanes","publication_year":2025,"publication_date":"2025-05-26","ids":{"openalex":"https://openalex.org/W7155367165","doi":"https://doi.org/10.1109/ets63895.2025.11049312"},"language":null,"primary_location":{"id":"doi:10.1109/ets63895.2025.11049312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets63895.2025.11049312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5134402993","display_name":"Zhaohong Lin","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Zhaohong Lin","raw_affiliation_strings":["Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5134414924","display_name":"Xiaole Cui","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Xiaole Cui","raw_affiliation_strings":["Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5119273544","display_name":"Juncheng Pu","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Juncheng Pu","raw_affiliation_strings":["Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China","institution_ids":["https://openalex.org/I20231570"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5134410491","display_name":"Huan Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I20231570","display_name":"Peking University","ror":"https://ror.org/02v51f717","country_code":"CN","type":"education","lineage":["https://openalex.org/I20231570"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Huan Yang","raw_affiliation_strings":["Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Peking University Shenzhen Graduate School,Key Lab of Integrated Microsystems,Shenzhen,China","institution_ids":["https://openalex.org/I20231570"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I20231570"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.3400000035762787,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11005","display_name":"Radiation Effects in Electronics","score":0.3400000035762787,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.13179999589920044,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.0957999974489212,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5317999720573425},{"id":"https://openalex.org/keywords/scheme","display_name":"Scheme (mathematics)","score":0.5213000178337097},{"id":"https://openalex.org/keywords/hexagonal-crystal-system","display_name":"Hexagonal crystal system","score":0.37790000438690186},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.33230000734329224},{"id":"https://openalex.org/keywords/printed-circuit-board","display_name":"Printed circuit board","score":0.3174999952316284}],"concepts":[{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5317999720573425},{"id":"https://openalex.org/C77618280","wikidata":"https://www.wikidata.org/wiki/Q1155772","display_name":"Scheme (mathematics)","level":2,"score":0.5213000178337097},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5102999806404114},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.42160001397132874},{"id":"https://openalex.org/C128765274","wikidata":"https://www.wikidata.org/wiki/Q663314","display_name":"Hexagonal crystal system","level":2,"score":0.37790000438690186},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.36809998750686646},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.361299991607666},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.33230000734329224},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32089999318122864},{"id":"https://openalex.org/C120793396","wikidata":"https://www.wikidata.org/wiki/Q173350","display_name":"Printed circuit board","level":2,"score":0.3174999952316284},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3109000027179718},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.29510000348091125},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.2727999985218048}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ets63895.2025.11049312","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets63895.2025.11049312","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320321001","display_name":"National Natural Science Foundation of China","ror":"https://ror.org/01h0zpd94"},{"id":"https://openalex.org/F4320337504","display_name":"Research and Development","ror":"https://ror.org/027s68j25"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":0,"referenced_works":[],"related_works":[],"abstract_inverted_index":{"The":[0,25,33,45],"chiplet-based":[1],"2.5D/3D":[2],"multi-die":[3],"integrated":[4],"chips":[5],"have":[6],"numerous":[7],"inter-die":[8],"interconnect":[9,52],"lanes,":[10,91],"which":[11,92,108],"may":[12],"suffer":[13],"from":[14],"the":[15,42,55,69,73,94,98,110,126,147],"faults":[16,26,65,128,142],"in":[17,30,116,143],"Through":[18],"Silicon":[19],"Vias":[20],"(TSVs)":[21],"or":[22],"micro":[23],"bumps.":[24],"are":[27,36,66],"usually":[28],"clustered":[29,99,127],"some":[31],"regions.":[32],"redundant":[34,62,90,134],"lanes":[35,49,63,87,115],"introduced":[37],"for":[38,97,125,140],"repairing,":[39],"to":[40],"maintain":[41],"product":[43],"yield.":[44],"hexagonal":[46],"array":[47],"of":[48,112,133],"offers":[50],"higher":[51,122],"density":[53],"than":[54,160],"rectangular":[56],"array,":[57],"but":[58],"it":[59],"requires":[60],"more":[61],"if":[64],"located":[67],"within":[68],"same":[70],"module.":[71],"In":[72],"Universal":[74],"Chiplet":[75],"Interconnect":[76],"Express":[77],"(UCIe)":[78],"standard,":[79],"each":[80],"Advanced":[81],"Package":[82],"module":[83],"contains":[84],"32":[85],"data":[86],"and":[88],"2":[89],"limit":[93],"repair":[95,106,123,152],"rate":[96,124,153],"faults.":[100],"This":[101],"work":[102],"proposes":[103],"a":[104,121,130,151],"UCIe-compatible":[105],"scheme":[107,149],"increases":[109],"probability":[111],"distributing":[113],"faulty":[114],"different":[117],"modules.":[118],"It":[119],"achieves":[120,150],"with":[129],"low":[131],"proportion":[132],"lanes.":[135],"Simulation":[136],"results":[137],"show":[138],"that":[139],"8":[141],"various":[144],"cluster":[145],"windows,":[146],"proposed":[148],"above":[154],"98%":[155],"while":[156],"consuming":[157],"less":[158],"area":[159],"previous":[161],"approaches.":[162]},"counts_by_year":[{"year":2026,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2026-04-24T00:00:00"}
