{"id":"https://openalex.org/W4283751350","doi":"https://doi.org/10.1109/ets54262.2022.9810466","title":"FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level","display_name":"FPGA Design Deobfuscation by Iterative LUT Modifications at Bitstream Level","publication_year":2022,"publication_date":"2022-05-23","ids":{"openalex":"https://openalex.org/W4283751350","doi":"https://doi.org/10.1109/ets54262.2022.9810466"},"language":"en","primary_location":{"id":"doi:10.1109/ets54262.2022.9810466","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets54262.2022.9810466","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5087700053","display_name":"Michail Moraitis","orcid":"https://orcid.org/0000-0002-0278-5986"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Michail Moraitis","raw_affiliation_strings":["Royal Institute of Technology (KTH),Department of Electrical Engineering,Stockholm,Sweden,196 40"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Royal Institute of Technology (KTH),Department of Electrical Engineering,Stockholm,Sweden,196 40","institution_ids":["https://openalex.org/I86987016"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5011438358","display_name":"Elena Dubrova","orcid":"https://orcid.org/0000-0001-7382-9408"},"institutions":[{"id":"https://openalex.org/I86987016","display_name":"KTH Royal Institute of Technology","ror":"https://ror.org/026vcq606","country_code":"SE","type":"education","lineage":["https://openalex.org/I86987016"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"Elena Dubrova","raw_affiliation_strings":["Royal Institute of Technology (KTH),Department of Electrical Engineering,Stockholm,Sweden,196 40"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Royal Institute of Technology (KTH),Department of Electrical Engineering,Stockholm,Sweden,196 40","institution_ids":["https://openalex.org/I86987016"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I86987016"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"12","issue":null,"first_page":"1","last_page":"2"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10951","display_name":"Cryptographic Implementations and Security","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11689","display_name":"Adversarial Robustness in Machine Learning","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bitstream","display_name":"Bitstream","score":0.8978614807128906},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8837568759918213},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8038088083267212},{"id":"https://openalex.org/keywords/netlist","display_name":"Netlist","score":0.7433054447174072},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6306287050247192},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5574303269386292},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4427656829357147},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.42579385638237},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.341473788022995},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32559865713119507},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.1833321452140808},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.1287883222103119},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.08741691708564758}],"concepts":[{"id":"https://openalex.org/C136695289","wikidata":"https://www.wikidata.org/wiki/Q415568","display_name":"Bitstream","level":3,"score":0.8978614807128906},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8837568759918213},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8038088083267212},{"id":"https://openalex.org/C177650935","wikidata":"https://www.wikidata.org/wiki/Q1760303","display_name":"Netlist","level":2,"score":0.7433054447174072},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6306287050247192},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5574303269386292},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4427656829357147},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.42579385638237},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.341473788022995},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32559865713119507},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.1833321452140808},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.1287883222103119},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.08741691708564758}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ets54262.2022.9810466","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets54262.2022.9810466","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2022 IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320316851","display_name":"KT","ror":"https://ror.org/043n4tt17"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1578574674","https://openalex.org/W2171546918","https://openalex.org/W2478604032","https://openalex.org/W2754409419","https://openalex.org/W2766071343","https://openalex.org/W2949797438","https://openalex.org/W2990238172","https://openalex.org/W3106531880","https://openalex.org/W3116341780","https://openalex.org/W3170159994","https://openalex.org/W4241352338","https://openalex.org/W6776294083"],"related_works":["https://openalex.org/W3127435654","https://openalex.org/W2919561762","https://openalex.org/W4319430423","https://openalex.org/W4390224957","https://openalex.org/W2145339442","https://openalex.org/W4323831234","https://openalex.org/W3009852985","https://openalex.org/W4243305727","https://openalex.org/W2544043553","https://openalex.org/W3217774925"],"abstract_inverted_index":{"We":[0],"present":[1],"an":[2,70],"algorithm":[3],"capable":[4],"of":[5,25,48,61,69],"defeating":[6],"SRAM":[7],"FPGA":[8,57],"design":[9,74],"obfuscation":[10],"methods":[11],"based":[12],"on":[13,66],"hardware":[14],"opaque":[15],"predicates.":[16],"This":[17],"is":[18,52,64],"achieved":[19],"by":[20],"ensuring":[21],"the":[22,40,46,56,67],"full":[23],"controllability":[24],"each":[26],"instantiated":[27],"look-up":[28],"table":[29],"input":[30],"via":[31],"iterative":[32],"bitstream":[33],"modifications.":[34],"Unlike":[35],"many":[36],"previous":[37],"deobfuscation":[38],"approaches,":[39],"presented":[41],"method":[42],"does":[43],"not":[44],"require":[45],"possession":[47],"a":[49,77],"netlist.":[50],"It":[51],"applied":[53],"directly":[54],"to":[55],"bitstream.":[58],"The":[59],"feasibility":[60],"our":[62],"approach":[63],"verified":[65],"example":[68],"obfuscated":[71],"SNOW":[72],"3G":[73],"implemented":[75],"in":[76],"Xilinx":[78],"Artix-7":[79],"FPGA.":[80]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}
