{"id":"https://openalex.org/W3176495762","doi":"https://doi.org/10.1109/ets50041.2021.9465464","title":"Convolutional Compaction-Based MRAM Fault Diagnosis","display_name":"Convolutional Compaction-Based MRAM Fault Diagnosis","publication_year":2021,"publication_date":"2021-05-24","ids":{"openalex":"https://openalex.org/W3176495762","doi":"https://doi.org/10.1109/ets50041.2021.9465464","mag":"3176495762"},"language":"en","primary_location":{"id":"doi:10.1109/ets50041.2021.9465464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets50041.2021.9465464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067384117","display_name":"Bartosz Grzelak","orcid":null},"institutions":[{"id":"https://openalex.org/I46597724","display_name":"Pozna\u0144 University of Technology","ror":"https://ror.org/00p7p3302","country_code":"PL","type":"education","lineage":["https://openalex.org/I46597724"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Bartosz Grzelak","raw_affiliation_strings":["Pozna\u0144 University of Technology, Pozna\u0144, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pozna\u0144 University of Technology, Pozna\u0144, Poland","institution_ids":["https://openalex.org/I46597724"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019406427","display_name":"Martin Keim","orcid":"https://orcid.org/0000-0002-0029-135X"},"institutions":[{"id":"https://openalex.org/I4210137693","display_name":"Siemens (United States)","ror":"https://ror.org/04axb7e79","country_code":"US","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210137693"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Martin Keim","raw_affiliation_strings":["Siemens Digital Industries Software, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Siemens Digital Industries Software, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210137693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5004438248","display_name":"Artur Pogiel","orcid":"https://orcid.org/0000-0001-5271-1566"},"institutions":[{"id":"https://openalex.org/I4210137693","display_name":"Siemens (United States)","ror":"https://ror.org/04axb7e79","country_code":"US","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210137693"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Artur Pogiel","raw_affiliation_strings":["Siemens Digital Industries Software, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Siemens Digital Industries Software, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210137693"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5080960636","display_name":"Janusz Rajski","orcid":"https://orcid.org/0000-0003-2124-447X"},"institutions":[{"id":"https://openalex.org/I4210137693","display_name":"Siemens (United States)","ror":"https://ror.org/04axb7e79","country_code":"US","type":"company","lineage":["https://openalex.org/I1325886976","https://openalex.org/I4210137693"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Janusz Rajski","raw_affiliation_strings":["Siemens Digital Industries Software, Wilsonville, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Siemens Digital Industries Software, Wilsonville, OR, USA","institution_ids":["https://openalex.org/I4210137693"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5072675590","display_name":"Jerzy Tyszer","orcid":"https://orcid.org/0000-0001-9722-2344"},"institutions":[{"id":"https://openalex.org/I46597724","display_name":"Pozna\u0144 University of Technology","ror":"https://ror.org/00p7p3302","country_code":"PL","type":"education","lineage":["https://openalex.org/I46597724"]}],"countries":["PL"],"is_corresponding":false,"raw_author_name":"Jerzy Tyszer","raw_affiliation_strings":["Pozna\u0144 University of Technology, Pozna\u0144, Poland"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Pozna\u0144 University of Technology, Pozna\u0144, Poland","institution_ids":["https://openalex.org/I46597724"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":"18","issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7423294186592102},{"id":"https://openalex.org/keywords/trimming","display_name":"Trimming","score":0.5671653747558594},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.5606973767280579},{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.5308875441551208},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4877394139766693},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.4795393943786621},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.46660158038139343},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4643592834472656},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.46068432927131653},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3566156029701233},{"id":"https://openalex.org/keywords/random-access-memory","display_name":"Random access memory","score":0.21330851316452026},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.15938881039619446}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7423294186592102},{"id":"https://openalex.org/C56951928","wikidata":"https://www.wikidata.org/wiki/Q3539213","display_name":"Trimming","level":2,"score":0.5671653747558594},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.5606973767280579},{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.5308875441551208},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4877394139766693},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.4795393943786621},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.46660158038139343},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4643592834472656},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.46068432927131653},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3566156029701233},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.21330851316452026},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.15938881039619446},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ets50041.2021.9465464","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets50041.2021.9465464","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2021 IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1601643892","https://openalex.org/W2101900253","https://openalex.org/W2105816698","https://openalex.org/W2106935654","https://openalex.org/W2122385695","https://openalex.org/W2162570610","https://openalex.org/W2909308379","https://openalex.org/W2944858442","https://openalex.org/W3040591402"],"related_works":["https://openalex.org/W2467235537","https://openalex.org/W4243755427","https://openalex.org/W1493074871","https://openalex.org/W2222099502","https://openalex.org/W2128287377","https://openalex.org/W1979067309","https://openalex.org/W2375590729","https://openalex.org/W2385024427","https://openalex.org/W2978797270","https://openalex.org/W2119025037"],"abstract_inverted_index":{"Spin-transfer":[0],"torque":[1],"magnetoresistive":[2],"random-access":[3],"memories":[4],"(STT-MRAMs)":[5],"are":[6,142],"gradually":[7],"superseding":[8],"conventional":[9],"SRAMs":[10],"as":[11,154,181],"last-level":[12],"cache":[13],"in":[14,25,113,145],"System-on-Chip":[15],"designs.":[16],"Their":[17],"manufacturing":[18],"process":[19],"includes":[20],"trimming":[21,44,59],"a":[22,51,58,65,73,91,101,120,134,137,169,173,184,190],"reference":[23],"resistance":[24],"STT-MRAM":[26,165],"modules":[27],"to":[28,133],"reliably":[29],"determine":[30],"the":[31,130,155,164],"logic":[32],"values":[33],"of":[34,47,50,57,68,71,76,80,108,123,129,179],"0":[35],"and":[36,93,126],"1":[37],"during":[38],"read":[39],"operations.":[40],"Typically,":[41],"an":[42,114,148],"on-chip":[43,149],"routine":[45],"consists":[46],"multiple":[48],"runs":[49],"test":[52,150],"algorithm":[53],"with":[54],"different":[55],"settings":[56],"port.":[60],"It":[61,117,159],"may":[62],"inherently":[63],"produce":[64],"large":[66],"number":[67],"mismatches.":[69],"Diagnosis":[70],"such":[72,153],"sizeable":[74],"volume":[75],"errors":[77],"by":[78,167],"means":[79],"existing":[81],"memory":[82,103,124],"built-in":[83],"self-test":[84],"(MBIST)":[85],"schemes":[86],"is":[87,160,172],"either":[88],"infeasible":[89],"or":[90],"time-consuming":[92],"expensive":[94],"process.":[95],"In":[96],"this":[97,177],"paper,":[98],"we":[99],"propose":[100],"new":[102],"fault":[104],"diagnosis":[105],"scheme":[106],"capable":[107],"handling":[109],"STT-MRAM-specific":[110],"error":[111],"rates":[112],"efficient":[115],"manner.":[116],"relies":[118],"on":[119],"convolutional":[121,170],"reduction":[122],"outputs":[125],"continuous":[127],"shifting":[128],"resultant":[131],"data":[132],"tester":[135],"through":[136],"few":[138],"output":[139,166],"channels":[140],"that":[141,162],"typically":[143],"available":[144],"designs":[146],"using":[147,168],"compression":[151],"technology,":[152],"embedded":[156],"deterministic":[157],"test.":[158],"shown":[161],"processing":[163],"compactor":[171],"preferable":[174],"solution":[175],"for":[176],"type":[178],"applications,":[180],"it":[182],"provides":[183],"high":[185],"diagnostic":[186],"resolution":[187],"while":[188],"incurring":[189],"low":[191],"hardware":[192],"overhead":[193],"over":[194],"traditional":[195],"MBIST":[196],"logic.":[197]},"counts_by_year":[],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}