{"id":"https://openalex.org/W2485178227","doi":"https://doi.org/10.1109/ets.2016.7519328","title":"Utilizing shared memory multi-cores to speed-up the ATPG process","display_name":"Utilizing shared memory multi-cores to speed-up the ATPG process","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2485178227","doi":"https://doi.org/10.1109/ets.2016.7519328","mag":"2485178227"},"language":"en","primary_location":{"id":"doi:10.1109/ets.2016.7519328","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2016.7519328","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21th IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019013823","display_name":"Stavros Hadjitheophanous","orcid":"https://orcid.org/0000-0002-9029-2101"},"institutions":[{"id":"https://openalex.org/I34771391","display_name":"University of Cyprus","ror":"https://ror.org/02qjrjx09","country_code":"CY","type":"education","lineage":["https://openalex.org/I34771391"]}],"countries":["CY"],"is_corresponding":false,"raw_author_name":"Stavros Hadjitheophanous","raw_affiliation_strings":["University of Cyprus, KIOS Research Center, Cyprus"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Cyprus, KIOS Research Center, Cyprus","institution_ids":["https://openalex.org/I34771391"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5077460840","display_name":"Stelios Neophytou","orcid":"https://orcid.org/0000-0001-5728-6845"},"institutions":[{"id":"https://openalex.org/I17389662","display_name":"University of Nicosia","ror":"https://ror.org/04v18t651","country_code":"CY","type":"education","lineage":["https://openalex.org/I17389662"]}],"countries":["CY"],"is_corresponding":false,"raw_author_name":"Stelios N. Neophytou","raw_affiliation_strings":["University of Nicosia, KIOS Research Center, Cyprus"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Nicosia, KIOS Research Center, Cyprus","institution_ids":["https://openalex.org/I17389662"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5063130153","display_name":"Maria K. Michael","orcid":"https://orcid.org/0000-0002-1943-6547"},"institutions":[{"id":"https://openalex.org/I34771391","display_name":"University of Cyprus","ror":"https://ror.org/02qjrjx09","country_code":"CY","type":"education","lineage":["https://openalex.org/I34771391"]}],"countries":["CY"],"is_corresponding":false,"raw_author_name":"Maria K. Michael","raw_affiliation_strings":["University of Cyprus, KIOS Research Center, Cyprus"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Cyprus, KIOS Research Center, Cyprus","institution_ids":["https://openalex.org/I34771391"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.2818,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.788899,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9955000281333923,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10743","display_name":"Software Testing and Debugging Techniques","score":0.9954000115394592,"subfield":{"id":"https://openalex.org/subfields/1712","display_name":"Software"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.7908210754394531},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7804965376853943},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.7216901779174805},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5964675545692444},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.5083188414573669},{"id":"https://openalex.org/keywords/set","display_name":"Set (abstract data type)","score":0.501474142074585},{"id":"https://openalex.org/keywords/speedup","display_name":"Speedup","score":0.43211910128593445},{"id":"https://openalex.org/keywords/shared-memory","display_name":"Shared memory","score":0.4181824028491974},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.4149720072746277},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3519566059112549},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.33725130558013916},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.10903948545455933},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.09587955474853516},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.09449723362922668}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.7908210754394531},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7804965376853943},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.7216901779174805},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5964675545692444},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.5083188414573669},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.501474142074585},{"id":"https://openalex.org/C68339613","wikidata":"https://www.wikidata.org/wiki/Q1549489","display_name":"Speedup","level":2,"score":0.43211910128593445},{"id":"https://openalex.org/C133875982","wikidata":"https://www.wikidata.org/wiki/Q764810","display_name":"Shared memory","level":2,"score":0.4181824028491974},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.4149720072746277},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3519566059112549},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.33725130558013916},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.10903948545455933},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.09587955474853516},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.09449723362922668},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ets.2016.7519328","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2016.7519328","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21th IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.41999998688697815}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1531040488","https://openalex.org/W1575233213","https://openalex.org/W1982628661","https://openalex.org/W1988641939","https://openalex.org/W2009690023","https://openalex.org/W2030467572","https://openalex.org/W2043080135","https://openalex.org/W2061411509","https://openalex.org/W2063193331","https://openalex.org/W2073590490","https://openalex.org/W2089540425","https://openalex.org/W2090601222","https://openalex.org/W2125029377","https://openalex.org/W2134895826","https://openalex.org/W2154508111","https://openalex.org/W2154934646","https://openalex.org/W2156640787","https://openalex.org/W4231973520"],"related_works":["https://openalex.org/W2058965144","https://openalex.org/W2164382479","https://openalex.org/W2146343568","https://openalex.org/W3012895752","https://openalex.org/W2045177269","https://openalex.org/W2116582200","https://openalex.org/W2089540425","https://openalex.org/W1580752477","https://openalex.org/W2061453039","https://openalex.org/W4205439893"],"abstract_inverted_index":{"A":[0],"new":[1],"test":[2,63,95],"generation":[3],"methodology":[4,80],"is":[5],"proposed":[6,41,79],"that":[7,44,68,77],"takes":[8],"advantage":[9],"of":[10,17,21,53,84],"shared":[11],"memory":[12],"multi-core":[13,89],"systems.":[14],"Appropriate":[15],"parallelization":[16],"the":[18,45,51,58,62,78],"main":[19],"steps":[20],"ATPG":[22],"allocates":[23],"resources":[24],"in":[25,37],"order":[26],"to":[27,67],"minimize":[28],"workload":[29],"duplication":[30],"and":[31],"multi-threading":[32],"race":[33],"contention,":[34],"often":[35],"encountered":[36],"parallel":[38],"implementations.":[39],"The":[40,73],"approach":[42],"ensures":[43],"obtained":[46,69],"acceleration":[47],"grows":[48],"linearly":[49],"with":[50],"number":[52],"processing":[54],"cores":[55],"and,":[56],"at":[57],"same":[59],"time,":[60],"keeps":[61],"set":[64,96],"size":[65],"close":[66],"by":[70],"serial":[71],"ATPG.":[72],"experimental":[74],"results":[75],"demonstrate":[76],"achieves":[81],"higher":[82],"degree":[83],"speed-up":[85],"than":[86],"comparable":[87],"state-of-the-art":[88],"based":[90],"tools,":[91],"while":[92],"maintains":[93],"similar":[94],"sizes.":[97]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":3},{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
