{"id":"https://openalex.org/W2487239614","doi":"https://doi.org/10.1109/ets.2016.7519310","title":"IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system","display_name":"IJTAG supported 3D DFT using chiplet-footprints for testing multi-chips active interposer system","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2487239614","doi":"https://doi.org/10.1109/ets.2016.7519310","mag":"2487239614"},"language":"en","primary_location":{"id":"doi:10.1109/ets.2016.7519310","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2016.7519310","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21th IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5037635558","display_name":"Jean Durupt","orcid":null},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I4210150049","display_name":"Laboratoire d'\u00c9lectronique des Technologies de l'Information","ror":"https://ror.org/04mf0wv34","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I4210117989","https://openalex.org/I4210150049"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Jean Durupt","raw_affiliation_strings":["Cea-Leti, Minatec Campus, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cea-Leti, Minatec Campus, Grenoble, France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I4210150049","https://openalex.org/I899635006"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5031216442","display_name":"Pascal Vivet","orcid":"https://orcid.org/0000-0002-7413-8243"},"institutions":[{"id":"https://openalex.org/I106785703","display_name":"Institut polytechnique de Grenoble","ror":"https://ror.org/05sbt2524","country_code":"FR","type":"education","lineage":["https://openalex.org/I106785703","https://openalex.org/I899635006"]},{"id":"https://openalex.org/I4210150049","display_name":"Laboratoire d'\u00c9lectronique des Technologies de l'Information","ror":"https://ror.org/04mf0wv34","country_code":"FR","type":"government","lineage":["https://openalex.org/I2738703131","https://openalex.org/I2738703131","https://openalex.org/I4210117989","https://openalex.org/I4210150049"]},{"id":"https://openalex.org/I899635006","display_name":"Universit\u00e9 Grenoble Alpes","ror":"https://ror.org/02rx3b187","country_code":"FR","type":"education","lineage":["https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Pascal Vivet","raw_affiliation_strings":["Cea-Leti, Minatec Campus, Grenoble, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Cea-Leti, Minatec Campus, Grenoble, France","institution_ids":["https://openalex.org/I106785703","https://openalex.org/I4210150049","https://openalex.org/I899635006"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052014650","display_name":"Juergen Schloeffel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"Juergen Schloeffel","raw_affiliation_strings":["Mentor Graphics, Hamburg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Hamburg, Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.0181,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.84899108,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11527","display_name":"3D IC and TSV technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/interposer","display_name":"Interposer","score":0.9783765077590942},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.588570237159729},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.5601125955581665},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5288147926330566},{"id":"https://openalex.org/keywords/three-dimensional-integrated-circuit","display_name":"Three-dimensional integrated circuit","score":0.5112950801849365},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.49291062355041504},{"id":"https://openalex.org/keywords/through-silicon-via","display_name":"Through-silicon via","score":0.4195868968963623},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3405725955963135},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2783483862876892},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.2654207646846771},{"id":"https://openalex.org/keywords/testability","display_name":"Testability","score":0.19003257155418396},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.14689186215400696},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.14362820982933044},{"id":"https://openalex.org/keywords/layer","display_name":"Layer (electronics)","score":0.12122860550880432},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.11971932649612427},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.07628288865089417}],"concepts":[{"id":"https://openalex.org/C158802814","wikidata":"https://www.wikidata.org/wiki/Q6056418","display_name":"Interposer","level":4,"score":0.9783765077590942},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.588570237159729},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.5601125955581665},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5288147926330566},{"id":"https://openalex.org/C59088047","wikidata":"https://www.wikidata.org/wiki/Q229370","display_name":"Three-dimensional integrated circuit","level":3,"score":0.5112950801849365},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.49291062355041504},{"id":"https://openalex.org/C45632049","wikidata":"https://www.wikidata.org/wiki/Q1578120","display_name":"Through-silicon via","level":3,"score":0.4195868968963623},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3405725955963135},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2783483862876892},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.2654207646846771},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.19003257155418396},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.14689186215400696},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.14362820982933044},{"id":"https://openalex.org/C2779227376","wikidata":"https://www.wikidata.org/wiki/Q6505497","display_name":"Layer (electronics)","level":2,"score":0.12122860550880432},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.11971932649612427},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.07628288865089417},{"id":"https://openalex.org/C159985019","wikidata":"https://www.wikidata.org/wiki/Q181790","display_name":"Composite material","level":1,"score":0.0},{"id":"https://openalex.org/C100460472","wikidata":"https://www.wikidata.org/wiki/Q2368605","display_name":"Etching (microfabrication)","level":3,"score":0.0},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ets.2016.7519310","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2016.7519310","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 21th IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.44999998807907104,"id":"https://metadata.un.org/sdg/9","display_name":"Industry, innovation and infrastructure"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1495055615","https://openalex.org/W1952859921","https://openalex.org/W2039336669","https://openalex.org/W2090396476","https://openalex.org/W2116426145","https://openalex.org/W2118445886","https://openalex.org/W2120351683","https://openalex.org/W2949580480","https://openalex.org/W4230995773","https://openalex.org/W6677637676","https://openalex.org/W6763539188"],"related_works":["https://openalex.org/W1990828594","https://openalex.org/W2011182927","https://openalex.org/W2310189477","https://openalex.org/W2333804548","https://openalex.org/W2543304869","https://openalex.org/W2019002696","https://openalex.org/W2072269247","https://openalex.org/W2047315796","https://openalex.org/W2002219888","https://openalex.org/W2896557720"],"abstract_inverted_index":{"In":[0,76],"order":[1,42],"to":[2,12,43,125,155],"increase":[3],"the":[4,48,51,103,126,136],"circuit":[5,17,128,150],"yield,":[6],"2.5D":[7,58],"technology":[8],"have":[9,60,69,141],"been":[10,62,71,142],"introduced":[11],"partition":[13],"a":[14,32,79,98,146],"single":[15],"large":[16],"in":[18,29,41],"multiple":[19],"circuits,":[20],"which":[21],"are":[22],"tested":[23],"before":[24],"bonding":[25],"and":[26,50,109,135,152,163],"then":[27],"assembled":[28],"3D":[30,52,67,80,127,138,147],"onto":[31,89,145],"passive":[33,161],"silicon":[34],"interposer.":[35,92],"Active":[36],"interposer":[37,49,149,157,160],"is":[38,83,95,110],"nowadays":[39],"envisioned":[40],"provide":[44],"added":[45],"values":[46],"within":[47],"complete":[53],"system.":[54],"The":[55,93,131],"testability":[56],"of":[57,106],"interposers":[59],"already":[61,70],"well":[63],"studied":[64],"but":[65],"no":[66],"DFT":[68],"proposed":[72,84,132],"for":[73,85],"active":[74,91,148,158],"interposers.":[75],"this":[77],"paper,":[78],"Design-for-Test":[81],"architecture":[82,134],"testing":[86],"multi-chips":[87],"stacked":[88],"an":[90],"3D-DFT":[94,133],"based":[96],"on":[97],"chiplet":[99,122],"footprint":[100],"architecture,":[101],"allowing":[102],"modular":[104],"test":[105,118,124,139,156],"any":[107],"chiplets,":[108],"implemented":[111],"using":[112],"IJTAG":[113],"IEEE1687":[114],"standard,":[115],"offering":[116],"easy":[117],"pattern":[119],"retargeting":[120],"from":[121],"pre-bond":[123],"final":[129],"test.":[130],"associated":[137],"flow":[140],"fully":[143],"applied":[144],"prototype":[151],"used":[153],"extensively":[154],"links,":[159],"links":[162],"all":[164],"embedded":[165],"memory":[166],"BIST":[167],"engines.":[168]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":2},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":2}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
