{"id":"https://openalex.org/W2029749084","doi":"https://doi.org/10.1109/ets.2013.6569379","title":"Variability-aware and fault-tolerant self-adaptive applications for many-core chips","display_name":"Variability-aware and fault-tolerant self-adaptive applications for many-core chips","publication_year":2013,"publication_date":"2013-05-01","ids":{"openalex":"https://openalex.org/W2029749084","doi":"https://doi.org/10.1109/ets.2013.6569379","mag":"2029749084"},"language":"en","primary_location":{"id":"doi:10.1109/ets.2013.6569379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2013.6569379","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5113588031","display_name":"Gilles Bizot","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Gilles Bizot","raw_affiliation_strings":["TIMA Laboratory, ARIS Team, France","TIMA Lab., ARIS Team, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, ARIS Team, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., ARIS Team, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066007278","display_name":"Fabien Chaix","orcid":"https://orcid.org/0009-0002-9438-6436"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Fabien Chaix","raw_affiliation_strings":["TIMA Laboratory, ARIS Team, France","TIMA Lab., ARIS Team, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, ARIS Team, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., ARIS Team, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109240766","display_name":"Nacer-Eddine Zergainoh","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Nacer-Eddine Zergainoh","raw_affiliation_strings":["TIMA Laboratory, ARIS Team, France","TIMA Lab., ARIS Team, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, ARIS Team, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., ARIS Team, France","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5039513293","display_name":"M. Nicolaidis","orcid":"https://orcid.org/0000-0003-1091-9339"},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Michael Nicolaidis","raw_affiliation_strings":["TIMA Laboratory, ARIS Team, France","TIMA Lab., ARIS Team, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, ARIS Team, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA Lab., ARIS Team, France","institution_ids":["https://openalex.org/I4210087012"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.0991216,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"1"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9975000023841858,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9948999881744385,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10715","display_name":"Distributed and Parallel Computing Systems","score":0.9919999837875366,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7554291486740112},{"id":"https://openalex.org/keywords/leverage","display_name":"Leverage (statistics)","score":0.7049531936645508},{"id":"https://openalex.org/keywords/fault-tolerance","display_name":"Fault tolerance","score":0.6204893589019775},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.5839938521385193},{"id":"https://openalex.org/keywords/many-core","display_name":"Many core","score":0.5408123135566711},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4860670864582062},{"id":"https://openalex.org/keywords/context","display_name":"Context (archaeology)","score":0.4475308060646057},{"id":"https://openalex.org/keywords/system-on-a-chip","display_name":"System on a chip","score":0.43663355708122253},{"id":"https://openalex.org/keywords/masking","display_name":"Masking (illustration)","score":0.4341677129268646},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4026932716369629},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3615712523460388},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.32256996631622314}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7554291486740112},{"id":"https://openalex.org/C153083717","wikidata":"https://www.wikidata.org/wiki/Q6535263","display_name":"Leverage (statistics)","level":2,"score":0.7049531936645508},{"id":"https://openalex.org/C63540848","wikidata":"https://www.wikidata.org/wiki/Q3140932","display_name":"Fault tolerance","level":2,"score":0.6204893589019775},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.5839938521385193},{"id":"https://openalex.org/C3020431745","wikidata":"https://www.wikidata.org/wiki/Q25325220","display_name":"Many core","level":2,"score":0.5408123135566711},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4860670864582062},{"id":"https://openalex.org/C2779343474","wikidata":"https://www.wikidata.org/wiki/Q3109175","display_name":"Context (archaeology)","level":2,"score":0.4475308060646057},{"id":"https://openalex.org/C118021083","wikidata":"https://www.wikidata.org/wiki/Q610398","display_name":"System on a chip","level":2,"score":0.43663355708122253},{"id":"https://openalex.org/C2777402240","wikidata":"https://www.wikidata.org/wiki/Q6783436","display_name":"Masking (illustration)","level":2,"score":0.4341677129268646},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4026932716369629},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3615712523460388},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.32256996631622314},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/ets.2013.6569379","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2013.6569379","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS)","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00842246v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00842246","pdf_url":null,"source":{"id":"https://openalex.org/S4306402512","display_name":"HAL (Le Centre pour la Communication Scientifique Directe)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I1294671590","host_organization_name":"Centre National de la Recherche Scientifique","host_organization_lineage":["https://openalex.org/I1294671590"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"18TH IEEE European Test Symposium (ETS), May 2013, Avignon, France. pp.162","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2089996875","https://openalex.org/W2120740899","https://openalex.org/W4297823684","https://openalex.org/W6678749433"],"related_works":["https://openalex.org/W2183032281","https://openalex.org/W2901915715","https://openalex.org/W2151327182","https://openalex.org/W2950848781","https://openalex.org/W4289293028","https://openalex.org/W4255057712","https://openalex.org/W4251458280","https://openalex.org/W2512412909","https://openalex.org/W1547865754","https://openalex.org/W2126398188"],"abstract_inverted_index":{"The":[0],"coming":[1],"era":[2],"of":[3,6,8,14,35,42],"chips":[4],"consisting":[5],"billions":[7],"gates":[9],"foreshadows":[10],"processors":[11],"containing":[12],"thousands":[13],"unreliable":[15,62],"cores.":[16],"In":[17,45],"this":[18,46],"context,":[19],"high":[20],"energy":[21],"efficiency":[22],"will":[23],"be":[24],"available,":[25],"under":[26],"the":[27,32,43],"constraint":[28],"that":[29],"applications":[30],"leverage":[31],"large":[33],"amount":[34],"computing":[36],"cores,":[37],"while":[38],"masking":[39],"frequent":[40],"faults":[41],"chip.":[44],"paper,":[47],"an":[48,61],"high-level":[49],"method":[50],"is":[51],"proposed":[52],"to":[53,69],"map":[54],"and":[55],"manage":[56],"a":[57],"parallel":[58],"application":[59],"on":[60,66],"many-cores":[63],"processor":[64],"System":[65],"Chip":[67],"subject":[68],"intra-die":[70],"variability.":[71]},"counts_by_year":[{"year":2024,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
