{"id":"https://openalex.org/W1992984946","doi":"https://doi.org/10.1109/ets.2012.6233046","title":"Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates","display_name":"Introduction to the defect-oriented cell-aware test methodology for significant reduction of DPPM rates","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W1992984946","doi":"https://doi.org/10.1109/ets.2012.6233046","mag":"1992984946"},"language":"en","primary_location":{"id":"doi:10.1109/ets.2012.6233046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2012.6233046","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 17th IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5065187948","display_name":"Friedrich Hapke","orcid":"https://orcid.org/0000-0001-8744-3039"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"F. Hapke","raw_affiliation_strings":["Mentor Graphics, Hamburg, Germany"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Hamburg, Germany","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5052014650","display_name":"Juergen Schloeffel","orcid":null},"institutions":[],"countries":[],"is_corresponding":false,"raw_author_name":"J. Schloeffel","raw_affiliation_strings":["Mentor Graphics, Hamburg, Germany"],"affiliations":[{"raw_affiliation_string":"Mentor Graphics, Hamburg, Germany","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5065187948"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.3205,"has_fulltext":false,"cited_by_count":50,"citation_normalized_percentile":{"value":0.8777403,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":94,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11338","display_name":"Advancements in Photolithography Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/automatic-test-pattern-generation","display_name":"Automatic test pattern generation","score":0.8151929974555969},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.675107479095459},{"id":"https://openalex.org/keywords/standard-cell","display_name":"Standard cell","score":0.671353816986084},{"id":"https://openalex.org/keywords/reduction","display_name":"Reduction (mathematics)","score":0.64913409948349},{"id":"https://openalex.org/keywords/test","display_name":"Test (biology)","score":0.542788028717041},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4878675937652588},{"id":"https://openalex.org/keywords/design-flow","display_name":"Design flow","score":0.4738519489765167},{"id":"https://openalex.org/keywords/design-for-testing","display_name":"Design for testing","score":0.45234882831573486},{"id":"https://openalex.org/keywords/fault-coverage","display_name":"Fault coverage","score":0.4220004975795746},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3086155652999878},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.3003169894218445},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1918063461780548},{"id":"https://openalex.org/keywords/integrated-circuit","display_name":"Integrated circuit","score":0.17869219183921814},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.15518608689308167},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.10717496275901794},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.09986609220504761}],"concepts":[{"id":"https://openalex.org/C17626397","wikidata":"https://www.wikidata.org/wiki/Q837455","display_name":"Automatic test pattern generation","level":3,"score":0.8151929974555969},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.675107479095459},{"id":"https://openalex.org/C78401558","wikidata":"https://www.wikidata.org/wiki/Q464496","display_name":"Standard cell","level":3,"score":0.671353816986084},{"id":"https://openalex.org/C111335779","wikidata":"https://www.wikidata.org/wiki/Q3454686","display_name":"Reduction (mathematics)","level":2,"score":0.64913409948349},{"id":"https://openalex.org/C2777267654","wikidata":"https://www.wikidata.org/wiki/Q3519023","display_name":"Test (biology)","level":2,"score":0.542788028717041},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4878675937652588},{"id":"https://openalex.org/C37135326","wikidata":"https://www.wikidata.org/wiki/Q931942","display_name":"Design flow","level":2,"score":0.4738519489765167},{"id":"https://openalex.org/C190874656","wikidata":"https://www.wikidata.org/wiki/Q5264347","display_name":"Design for testing","level":3,"score":0.45234882831573486},{"id":"https://openalex.org/C126953365","wikidata":"https://www.wikidata.org/wiki/Q5438152","display_name":"Fault coverage","level":3,"score":0.4220004975795746},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3086155652999878},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.3003169894218445},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1918063461780548},{"id":"https://openalex.org/C530198007","wikidata":"https://www.wikidata.org/wiki/Q80831","display_name":"Integrated circuit","level":2,"score":0.17869219183921814},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.15518608689308167},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.10717496275901794},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.09986609220504761},{"id":"https://openalex.org/C151730666","wikidata":"https://www.wikidata.org/wiki/Q7205","display_name":"Paleontology","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0},{"id":"https://openalex.org/C51234621","wikidata":"https://www.wikidata.org/wiki/Q2149495","display_name":"Testability","level":2,"score":0.0},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0},{"id":"https://openalex.org/C86803240","wikidata":"https://www.wikidata.org/wiki/Q420","display_name":"Biology","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ets.2012.6233046","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2012.6233046","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 17th IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4699999988079071,"id":"https://metadata.un.org/sdg/4","display_name":"Quality Education"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":16,"referenced_works":["https://openalex.org/W1961775031","https://openalex.org/W2034030717","https://openalex.org/W2061946964","https://openalex.org/W2086926157","https://openalex.org/W2096007426","https://openalex.org/W2098160130","https://openalex.org/W2102556246","https://openalex.org/W2118856265","https://openalex.org/W2119277411","https://openalex.org/W2120956034","https://openalex.org/W2124692465","https://openalex.org/W2152125778","https://openalex.org/W2169375167","https://openalex.org/W2170907629","https://openalex.org/W2171896075","https://openalex.org/W3139956757"],"related_works":["https://openalex.org/W2091833418","https://openalex.org/W2913077774","https://openalex.org/W4256030018","https://openalex.org/W2145089576","https://openalex.org/W2021253405","https://openalex.org/W1986228509","https://openalex.org/W2147400189","https://openalex.org/W1600468096","https://openalex.org/W2340957901","https://openalex.org/W2543176856"],"abstract_inverted_index":{"This":[0,14],"tutorial":[1,35],"will":[2,36],"give":[3],"an":[4,50],"introduction":[5],"to":[6,66,85],"a":[7,46,80,96],"new":[8,15,69],"defect-oriented":[9],"test":[10,88,93,105],"method":[11,17],"called":[12],"cell-aware.":[13],"cell-aware":[16,30,40,63,70,91],"takes":[18],"the":[19,29,38,62,68],"layout":[20,47],"of":[21,45,55,118],"standard":[22],"library":[23,32,41,72],"cells":[24],"into":[25],"account":[26],"when":[27],"creating":[28],"ATPG":[31,71],"view.":[33],"The":[34],"cover":[37],"whole":[39],"characterization":[42],"flow":[43,84],"consisting":[44],"extraction":[48],"step,":[49],"analog":[51],"fault":[52],"simulation":[53],"step":[54,65],"all":[56],"cell-internal":[57],"bridges":[58],"and":[59,61],"opens":[60],"synthesis":[64],"create":[67],"views,":[73],"which":[74],"finally":[75],"can":[76],"be":[77],"used":[78],"in":[79],"normal":[81],"chip":[82],"design":[83],"generate":[86],"production":[87,92,104],"patterns.":[89,102],"These":[90],"patterns":[94],"have":[95],"significantly":[97],"higher":[98],"quality":[99],"than":[100],"state-of-the-art":[101],"Finally,":[103],"results":[106],"from":[107],"several":[108],"hundred":[109],"thousand":[110],"tested":[111],"IC's":[112],"are":[113],"presented":[114],"showing":[115],"significant":[116],"reduction":[117],"DPPM":[119],"rates.":[120]},"counts_by_year":[{"year":2025,"cited_by_count":7},{"year":2024,"cited_by_count":5},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":8},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":5},{"year":2018,"cited_by_count":2},{"year":2016,"cited_by_count":2},{"year":2014,"cited_by_count":5},{"year":2013,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
