{"id":"https://openalex.org/W2147405966","doi":"https://doi.org/10.1109/ets.2012.6233022","title":"Indirect method for random jitter measurement on SoCs using critical path characterization","display_name":"Indirect method for random jitter measurement on SoCs using critical path characterization","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W2147405966","doi":"https://doi.org/10.1109/ets.2012.6233022","mag":"2147405966"},"language":"en","primary_location":{"id":"doi:10.1109/ets.2012.6233022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2012.6233022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 17th IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5100415738","display_name":"Jae Wook Lee","orcid":"https://orcid.org/0000-0002-8756-0195"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Jae Wook Lee","raw_affiliation_strings":["Intel Corporation, Austin, TX, USA","Intel Corp., Austin, TX 78746"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Austin, TX, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Intel Corp., Austin, TX 78746","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5019332672","display_name":"Ji Hwan Chun","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ji Hwan Chun","raw_affiliation_strings":["Intel Corporation, Santa Clara, CA, USA"],"affiliations":[{"raw_affiliation_string":"Intel Corporation, Santa Clara, CA, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5068070739","display_name":"Jacob A. Abraham","orcid":"https://orcid.org/0000-0002-5336-5631"},"institutions":[{"id":"https://openalex.org/I86519309","display_name":"The University of Texas at Austin","ror":"https://ror.org/00hj54h04","country_code":"US","type":"education","lineage":["https://openalex.org/I86519309"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. A. Abraham","raw_affiliation_strings":["Computer Engineering Research Center, University of Texas, Austin, Austin, TX, USA","Computer Engineering Research Center, The University of Texas at Austin, Austin, TX 78712#TAB#"],"affiliations":[{"raw_affiliation_string":"Computer Engineering Research Center, University of Texas, Austin, Austin, TX, USA","institution_ids":["https://openalex.org/I86519309"]},{"raw_affiliation_string":"Computer Engineering Research Center, The University of Texas at Austin, Austin, TX 78712#TAB#","institution_ids":["https://openalex.org/I86519309"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5100415738"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.16975829,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.9557387828826904},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5692253112792969},{"id":"https://openalex.org/keywords/microprocessor","display_name":"Microprocessor","score":0.5662640333175659},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5470961928367615},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4832352101802826},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4793872833251953},{"id":"https://openalex.org/keywords/critical-path-method","display_name":"Critical path method","score":0.45633643865585327},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.44471290707588196},{"id":"https://openalex.org/keywords/standard-deviation","display_name":"Standard deviation","score":0.4299926161766052},{"id":"https://openalex.org/keywords/root-mean-square","display_name":"Root mean square","score":0.4251478910446167},{"id":"https://openalex.org/keywords/real-time-computing","display_name":"Real-time computing","score":0.33072909712791443},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2256309688091278},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.21449965238571167},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20550602674484253},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1880245804786682},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.18326091766357422},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10445109009742737},{"id":"https://openalex.org/keywords/statistics","display_name":"Statistics","score":0.08470454812049866}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.9557387828826904},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5692253112792969},{"id":"https://openalex.org/C2780728072","wikidata":"https://www.wikidata.org/wiki/Q5297","display_name":"Microprocessor","level":2,"score":0.5662640333175659},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5470961928367615},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4832352101802826},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4793872833251953},{"id":"https://openalex.org/C115874739","wikidata":"https://www.wikidata.org/wiki/Q825377","display_name":"Critical path method","level":2,"score":0.45633643865585327},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.44471290707588196},{"id":"https://openalex.org/C22679943","wikidata":"https://www.wikidata.org/wiki/Q159375","display_name":"Standard deviation","level":2,"score":0.4299926161766052},{"id":"https://openalex.org/C71907059","wikidata":"https://www.wikidata.org/wiki/Q223323","display_name":"Root mean square","level":2,"score":0.4251478910446167},{"id":"https://openalex.org/C79403827","wikidata":"https://www.wikidata.org/wiki/Q3988","display_name":"Real-time computing","level":1,"score":0.33072909712791443},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2256309688091278},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.21449965238571167},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20550602674484253},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1880245804786682},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.18326091766357422},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10445109009742737},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.08470454812049866},{"id":"https://openalex.org/C201995342","wikidata":"https://www.wikidata.org/wiki/Q682496","display_name":"Systems engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/ets.2012.6233022","is_oa":false,"landing_page_url":"https://doi.org/10.1109/ets.2012.6233022","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 17th IEEE European Test Symposium (ETS)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.41999998688697815,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":19,"referenced_works":["https://openalex.org/W1568407911","https://openalex.org/W2075400577","https://openalex.org/W2104751464","https://openalex.org/W2106085401","https://openalex.org/W2110852606","https://openalex.org/W2112747772","https://openalex.org/W2122426826","https://openalex.org/W2126621570","https://openalex.org/W2129904319","https://openalex.org/W2130704241","https://openalex.org/W2141028418","https://openalex.org/W2154665706","https://openalex.org/W2162364319","https://openalex.org/W2162547872","https://openalex.org/W2164729680","https://openalex.org/W4237720872","https://openalex.org/W4246168672","https://openalex.org/W4247373393","https://openalex.org/W6679004695"],"related_works":["https://openalex.org/W2121182846","https://openalex.org/W2315668284","https://openalex.org/W2155789024","https://openalex.org/W2109491806","https://openalex.org/W3213608175","https://openalex.org/W1994021281","https://openalex.org/W2139484866","https://openalex.org/W2155236300","https://openalex.org/W2370061661","https://openalex.org/W1574257586"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,29,45,78,91],"new":[4],"method":[5,43],"for":[6],"random":[7,62],"jitter":[8,63,99,109],"measurement":[9],"on":[10],"systems-on-a-chip":[11],"(SoCs)":[12],"by":[13,126],"exploiting":[14],"shmoo":[15,88],"plotting":[16],"in":[17,69,84,101],"automatic":[18],"test":[19,33],"equipment":[20],"(ATE).":[21],"After":[22],"finding":[23],"the":[24,41,54,61,65,70,85,87,98,102,107,132],"maximum":[25],"operating":[26],"frequency":[27,79],"of":[28,60,64,131],"microprocessor":[30],"using":[31,129],"functional":[32],"patterns":[34],"that":[35,110],"can":[36,96],"sensitize":[37],"its":[38],"critical":[39,112],"paths,":[40],"proposed":[42,116],"constructs":[44],"cumulative":[46],"distribution":[47],"function":[48],"(CDF)":[49],"whose":[50],"standard":[51],"deviation":[52],"represents":[53],"root":[55],"mean":[56],"square":[57],"(RMS)":[58],"value":[59],"clock":[66,103],"signals":[67],"used":[68],"microprocessor.":[71],"By":[72],"leveraging":[73],"tester":[74],"period":[75,93],"resolution":[76],"with":[77,90,120],"multiplying":[80],"phase-locked":[81],"loop":[82],"(PLL)":[83],"SoC,":[86],"plot":[89],"fine":[92],"step":[94],"size":[95],"detect":[97],"component":[100],"signal,":[104],"which":[105],"reflects":[106],"actual":[108],"most":[111],"paths":[113],"undergo.":[114],"The":[115],"idea":[117],"was":[118,124],"verified":[119],"circuit-level":[121],"simulations,":[122],"and":[123],"validated":[125],"silicon":[127],"measurements":[128],"one":[130],"latest":[133],"SoC":[134],"products.":[135]},"counts_by_year":[],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
