{"id":"https://openalex.org/W1970173028","doi":"https://doi.org/10.1109/etfa.2011.6059176","title":"WCET analysis considering contention on memory bus in COTS-based multicores","display_name":"WCET analysis considering contention on memory bus in COTS-based multicores","publication_year":2011,"publication_date":"2011-09-01","ids":{"openalex":"https://openalex.org/W1970173028","doi":"https://doi.org/10.1109/etfa.2011.6059176","mag":"1970173028"},"language":"en","primary_location":{"id":"doi:10.1109/etfa.2011.6059176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/etfa.2011.6059176","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ETFA2011","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5041319859","display_name":"Dakshina Dasari","orcid":"https://orcid.org/0000-0002-6130-349X"},"institutions":[{"id":"https://openalex.org/I83863532","display_name":"Polytechnic Institute of Porto","ror":"https://ror.org/04988re48","country_code":"PT","type":"education","lineage":["https://openalex.org/I83863532"]}],"countries":["PT"],"is_corresponding":true,"raw_author_name":"Dakshina Dasari","raw_affiliation_strings":["CISTER-ISEP Research Centre, Polytechnic Institute of Porto, Portugal"],"affiliations":[{"raw_affiliation_string":"CISTER-ISEP Research Centre, Polytechnic Institute of Porto, Portugal","institution_ids":["https://openalex.org/I83863532"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101883269","display_name":"Vincent N\u00e9lis","orcid":"https://orcid.org/0000-0002-2955-0503"},"institutions":[{"id":"https://openalex.org/I83863532","display_name":"Polytechnic Institute of Porto","ror":"https://ror.org/04988re48","country_code":"PT","type":"education","lineage":["https://openalex.org/I83863532"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"Vincent Nelis","raw_affiliation_strings":["CISTER-ISEP Research Centre, Polytechnic Institute of Porto, Portugal"],"affiliations":[{"raw_affiliation_string":"CISTER-ISEP Research Centre, Polytechnic Institute of Porto, Portugal","institution_ids":["https://openalex.org/I83863532"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5111558021","display_name":"Bj\u00f6rn Andersson","orcid":"https://orcid.org/0000-0002-4718-5722"},"institutions":[{"id":"https://openalex.org/I83863532","display_name":"Polytechnic Institute of Porto","ror":"https://ror.org/04988re48","country_code":"PT","type":"education","lineage":["https://openalex.org/I83863532"]},{"id":"https://openalex.org/I74973139","display_name":"Carnegie Mellon University","ror":"https://ror.org/05x2bcf33","country_code":"US","type":"education","lineage":["https://openalex.org/I74973139"]},{"id":"https://openalex.org/I114772536","display_name":"Software Engineering Institute","ror":"https://ror.org/01xqjjn94","country_code":"US","type":"facility","lineage":["https://openalex.org/I114772536","https://openalex.org/I74973139"]}],"countries":["PT","US"],"is_corresponding":false,"raw_author_name":"Bjorn Andersson","raw_affiliation_strings":["CISTER-ISEP Research Centre, Polytechnic Institute of Porto, Portugal","Software Engineering Institute, Carnegie Mellon University, USA"],"affiliations":[{"raw_affiliation_string":"CISTER-ISEP Research Centre, Polytechnic Institute of Porto, Portugal","institution_ids":["https://openalex.org/I83863532"]},{"raw_affiliation_string":"Software Engineering Institute, Carnegie Mellon University, USA","institution_ids":["https://openalex.org/I114772536","https://openalex.org/I74973139"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5041319859"],"corresponding_institution_ids":["https://openalex.org/I83863532"],"apc_list":null,"apc_paid":null,"fwci":0.5135,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.64619775,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"4"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10933","display_name":"Real-Time Systems Scheduling","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9969000220298767,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10772","display_name":"Distributed systems and fault tolerance","score":0.9951000213623047,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8692876696586609},{"id":"https://openalex.org/keywords/multi-core-processor","display_name":"Multi-core processor","score":0.7891976833343506},{"id":"https://openalex.org/keywords/execution-time","display_name":"Execution time","score":0.5617297291755676},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.5582510232925415},{"id":"https://openalex.org/keywords/field","display_name":"Field (mathematics)","score":0.5116553902626038},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.48510634899139404},{"id":"https://openalex.org/keywords/worst-case-execution-time","display_name":"Worst-case execution time","score":0.44694656133651733},{"id":"https://openalex.org/keywords/core","display_name":"Core (optical fiber)","score":0.44102543592453003},{"id":"https://openalex.org/keywords/distributed-computing","display_name":"Distributed computing","score":0.3818802833557129},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.33402764797210693}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8692876696586609},{"id":"https://openalex.org/C78766204","wikidata":"https://www.wikidata.org/wiki/Q555032","display_name":"Multi-core processor","level":2,"score":0.7891976833343506},{"id":"https://openalex.org/C2989134064","wikidata":"https://www.wikidata.org/wiki/Q288510","display_name":"Execution time","level":2,"score":0.5617297291755676},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.5582510232925415},{"id":"https://openalex.org/C9652623","wikidata":"https://www.wikidata.org/wiki/Q190109","display_name":"Field (mathematics)","level":2,"score":0.5116553902626038},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.48510634899139404},{"id":"https://openalex.org/C200130814","wikidata":"https://www.wikidata.org/wiki/Q362858","display_name":"Worst-case execution time","level":3,"score":0.44694656133651733},{"id":"https://openalex.org/C2164484","wikidata":"https://www.wikidata.org/wiki/Q5170150","display_name":"Core (optical fiber)","level":2,"score":0.44102543592453003},{"id":"https://openalex.org/C120314980","wikidata":"https://www.wikidata.org/wiki/Q180634","display_name":"Distributed computing","level":1,"score":0.3818802833557129},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.33402764797210693},{"id":"https://openalex.org/C202444582","wikidata":"https://www.wikidata.org/wiki/Q837863","display_name":"Pure mathematics","level":1,"score":0.0},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/etfa.2011.6059176","is_oa":false,"landing_page_url":"https://doi.org/10.1109/etfa.2011.6059176","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ETFA2011","raw_type":"proceedings-article"},{"id":"pmh:oai:recipp.ipp.pt:10400.22/3743","is_oa":false,"landing_page_url":"http://hdl.handle.net/10400.22/3743","pdf_url":null,"source":{"id":"https://openalex.org/S4306401177","display_name":"Scientific Repository of the Polytechnic Institute of Porto (The Polytechnic Institute of Porto)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I83863532","host_organization_name":"Polytechnic Institute of Porto","host_organization_lineage":["https://openalex.org/I83863532"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"journal article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1515422725","https://openalex.org/W1544222953","https://openalex.org/W1973284712","https://openalex.org/W2076285066","https://openalex.org/W2099697479","https://openalex.org/W2135362168","https://openalex.org/W2148016091","https://openalex.org/W2153027637","https://openalex.org/W2986939591","https://openalex.org/W3142152400"],"related_works":["https://openalex.org/W1515433387","https://openalex.org/W1484796814","https://openalex.org/W1663166257","https://openalex.org/W2507397068","https://openalex.org/W2537786014","https://openalex.org/W52215546","https://openalex.org/W3023876411","https://openalex.org/W2159593428","https://openalex.org/W3198992024","https://openalex.org/W2353696478"],"abstract_inverted_index":{"The":[0],"usage":[1],"of":[2,11,33,36,51,98],"COTS-based":[3,78],"multicores":[4],"is":[5,19],"becoming":[6],"widespread":[7],"in":[8,75],"the":[9,31,34,37,46,52,64,69,96,99],"field":[10],"embedded":[12],"systems.":[13],"Providing":[14],"realtime":[15],"guarantees":[16],"at":[17],"design-time":[18],"a":[20,55,72,76,86],"pre-requisite":[21],"to":[22,40,90],"deploy":[23],"real-time":[24],"systems":[25],"on":[26,45,95,105],"these":[27],"multicores.":[28],"This":[29],"necessitates":[30],"consideration":[32],"impact":[35],"contention":[38],"due":[39],"shared":[41],"low-level":[42],"hardware":[43],"resources":[44],"Worst-Case":[47],"Execution":[48],"Time":[49],"(WCET)":[50],"tasks.":[53],"As":[54],"step":[56],"towards":[57],"this":[58,60],"aim,":[59],"paper":[61],"first":[62],"identifies":[63],"different":[65,106],"factors":[66],"that":[67],"make":[68],"WCET":[70,97],"analysis":[71],"challenging":[73],"problem":[74],"typical":[77],"multicore":[79],"system.":[80],"Then,":[81],"we":[82],"propose":[83],"and":[84],"prove,":[85],"mathematically":[87],"correct":[88],"method":[89],"determine":[91],"tight":[92],"upper":[93],"bounds":[94],"tasks,":[100],"when":[101],"they":[102],"are":[103],"co-scheduled":[104],"cores.":[107]},"counts_by_year":[{"year":2017,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}