{"id":"https://openalex.org/W2155149905","doi":"https://doi.org/10.1109/estmed.2008.4696998","title":"Optimal address register allocation for arrays in DSP applications","display_name":"Optimal address register allocation for arrays in DSP applications","publication_year":2008,"publication_date":"2008-10-01","ids":{"openalex":"https://openalex.org/W2155149905","doi":"https://doi.org/10.1109/estmed.2008.4696998","mag":"2155149905"},"language":"en","primary_location":{"id":"doi:10.1109/estmed.2008.4696998","is_oa":false,"landing_page_url":"https://doi.org/10.1109/estmed.2008.4696998","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005484411","display_name":"Hassan Salamy","orcid":"https://orcid.org/0000-0003-1314-1702"},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Hassan Salamy","raw_affiliation_strings":["Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, LA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, LA, USA","institution_ids":["https://openalex.org/I121820613"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057117526","display_name":"J. Ramanujam","orcid":"https://orcid.org/0000-0002-4349-1327"},"institutions":[{"id":"https://openalex.org/I121820613","display_name":"Louisiana State University","ror":"https://ror.org/05ect4e57","country_code":"US","type":"education","lineage":["https://openalex.org/I121820613"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"J. Ramanujam","raw_affiliation_strings":["Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, LA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical and Computer Engineering and Center for Computation and Technology, Louisiana State University, Baton Rouge, LA, USA","institution_ids":["https://openalex.org/I121820613"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I121820613"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.13130855,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":"8","issue":null,"first_page":"67","last_page":"72"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8601093292236328},{"id":"https://openalex.org/keywords/register-allocation","display_name":"Register allocation","score":0.8377829790115356},{"id":"https://openalex.org/keywords/digital-signal-processing","display_name":"Digital signal processing","score":0.6764500141143799},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.6646015644073486},{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6367884278297424},{"id":"https://openalex.org/keywords/code-generation","display_name":"Code generation","score":0.500173807144165},{"id":"https://openalex.org/keywords/code","display_name":"Code (set theory)","score":0.4899405837059021},{"id":"https://openalex.org/keywords/processor-register","display_name":"Processor register","score":0.46780872344970703},{"id":"https://openalex.org/keywords/program-optimization","display_name":"Program optimization","score":0.4599730968475342},{"id":"https://openalex.org/keywords/integer","display_name":"Integer (computer science)","score":0.44569870829582214},{"id":"https://openalex.org/keywords/digital-signal-processor","display_name":"Digital signal processor","score":0.44422924518585205},{"id":"https://openalex.org/keywords/integer-programming","display_name":"Integer programming","score":0.412209153175354},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.3282991051673889},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2263120710849762},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.20104098320007324},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.19775837659835815},{"id":"https://openalex.org/keywords/memory-address","display_name":"Memory address","score":0.1707441508769989},{"id":"https://openalex.org/keywords/key","display_name":"Key (lock)","score":0.10319381952285767},{"id":"https://openalex.org/keywords/programming-language","display_name":"Programming language","score":0.0913647711277008},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.0836707353591919}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8601093292236328},{"id":"https://openalex.org/C128916667","wikidata":"https://www.wikidata.org/wiki/Q1343660","display_name":"Register allocation","level":3,"score":0.8377829790115356},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.6764500141143799},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.6646015644073486},{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6367884278297424},{"id":"https://openalex.org/C133162039","wikidata":"https://www.wikidata.org/wiki/Q1061077","display_name":"Code generation","level":3,"score":0.500173807144165},{"id":"https://openalex.org/C2776760102","wikidata":"https://www.wikidata.org/wiki/Q5139990","display_name":"Code (set theory)","level":3,"score":0.4899405837059021},{"id":"https://openalex.org/C2871975","wikidata":"https://www.wikidata.org/wiki/Q187466","display_name":"Processor register","level":4,"score":0.46780872344970703},{"id":"https://openalex.org/C139571649","wikidata":"https://www.wikidata.org/wiki/Q1156793","display_name":"Program optimization","level":3,"score":0.4599730968475342},{"id":"https://openalex.org/C97137487","wikidata":"https://www.wikidata.org/wiki/Q729138","display_name":"Integer (computer science)","level":2,"score":0.44569870829582214},{"id":"https://openalex.org/C161611012","wikidata":"https://www.wikidata.org/wiki/Q106370","display_name":"Digital signal processor","level":3,"score":0.44422924518585205},{"id":"https://openalex.org/C56086750","wikidata":"https://www.wikidata.org/wiki/Q6042592","display_name":"Integer programming","level":2,"score":0.412209153175354},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.3282991051673889},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2263120710849762},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.20104098320007324},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.19775837659835815},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.1707441508769989},{"id":"https://openalex.org/C26517878","wikidata":"https://www.wikidata.org/wiki/Q228039","display_name":"Key (lock)","level":2,"score":0.10319381952285767},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0913647711277008},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0836707353591919},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.0},{"id":"https://openalex.org/C177264268","wikidata":"https://www.wikidata.org/wiki/Q1514741","display_name":"Set (abstract data type)","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/estmed.2008.4696998","is_oa":false,"landing_page_url":"https://doi.org/10.1109/estmed.2008.4696998","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2008 IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia","raw_type":"proceedings-article"},{"id":"pmh:oai:repository.lsu.edu:eecs_pubs-2620","is_oa":false,"landing_page_url":"https://repository.lsu.edu/eecs_pubs/1618","pdf_url":null,"source":{"id":"https://openalex.org/S4210169993","display_name":"Civil War Book Review","issn_l":"1528-6592","issn":["1528-6592"],"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/P4310315936","host_organization_name":"Louisiana State University","host_organization_lineage":["https://openalex.org/P4310315936"],"host_organization_lineage_names":["Louisiana State University"],"type":"journal"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Faculty Publications","raw_type":"text"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":24,"referenced_works":["https://openalex.org/W34890220","https://openalex.org/W1513400187","https://openalex.org/W1969897078","https://openalex.org/W1981350555","https://openalex.org/W1981718090","https://openalex.org/W1999095027","https://openalex.org/W2023335354","https://openalex.org/W2034350206","https://openalex.org/W2045035683","https://openalex.org/W2086980357","https://openalex.org/W2099890221","https://openalex.org/W2103552119","https://openalex.org/W2104891966","https://openalex.org/W2107413305","https://openalex.org/W2108861994","https://openalex.org/W2157529519","https://openalex.org/W2160209808","https://openalex.org/W2165899471","https://openalex.org/W4234197339","https://openalex.org/W4243705787","https://openalex.org/W4247361710","https://openalex.org/W4248400866","https://openalex.org/W4250060586","https://openalex.org/W6683518376"],"related_works":["https://openalex.org/W2269159438","https://openalex.org/W4312357863","https://openalex.org/W2251007391","https://openalex.org/W61798728","https://openalex.org/W2373710463","https://openalex.org/W1482854495","https://openalex.org/W2075496182","https://openalex.org/W28761524","https://openalex.org/W2148077795","https://openalex.org/W4243103922"],"abstract_inverted_index":{"Optimizing":[0],"the":[1,57,62,90,100,116,133,156,166],"code":[2,20,123],"size":[3],"of":[4,72,83,92,145,158],"a":[5,11,35,80,138,142],"digital":[6,26],"signal":[7,27],"processing":[8],"application":[9],"is":[10,51,60,128],"crucial":[12],"step":[13],"in":[14,45,141,165],"generating":[15],"high":[16],"quality":[17],"and":[18,34],"efficient":[19],"for":[21,115,147],"embedded":[22,149],"systems.":[23],"Most":[24],"modern":[25],"processors":[28],"(DSPs)":[29],"provide":[30],"multiple":[31],"address":[32,37,43,53,59,87,94,117],"registers":[33,88],"dedicated":[36],"generation":[38,44],"unit":[39],"(AGU)":[40],"that":[41],"provides":[42],"parallel":[46],"to":[47,74,86,131,136,162],"instruction":[48],"execution.":[49],"There":[50],"no":[52],"computation":[54],"overhead":[55],"if":[56],"next":[58],"within":[61,77],"auto-modify":[63],"range.":[64],"Many":[65],"DSP":[66],"algorithms":[67],"have":[68],"an":[69,108],"iterative":[70],"pattern":[71],"references":[73,85],"array":[75,84],"elements":[76],"loops.":[78],"Thus,":[79],"careful":[81],"assignment":[82],"reduces":[89],"number":[91],"explicit":[93],"register":[95,118],"instructions":[96],"as":[97,99],"well":[98],"execution":[101],"cycles.":[102],"In":[103],"this":[104],"paper,":[105],"we":[106],"present":[107],"optimal":[109],"integer":[110],"linear":[111],"programming":[112],"(ILP)":[113],"formulation":[114],"allocation":[119],"problem":[120,135],"(ARA)":[121],"with":[122],"reconstructing":[124],"techniques.":[125],"Genetic":[126],"algorithm":[127],"also":[129],"used":[130],"solve":[132],"ARA":[134],"get":[137],"near-optimal":[139],"solution":[140],"reasonable":[143],"amount":[144],"time":[146],"big":[148],"applications.":[150],"Results":[151],"on":[152],"several":[153],"benchmarks":[154],"show":[155],"effectiveness":[157],"our":[159],"techniques":[160,164],"compared":[161],"other":[163],"literature.":[167]},"counts_by_year":[],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}