{"id":"https://openalex.org/W1971372758","doi":"https://doi.org/10.1109/estimedia.2012.6507023","title":"Memory-centric VDF graph transformations for practical FPGA implementation","display_name":"Memory-centric VDF graph transformations for practical FPGA implementation","publication_year":2012,"publication_date":"2012-10-01","ids":{"openalex":"https://openalex.org/W1971372758","doi":"https://doi.org/10.1109/estimedia.2012.6507023","mag":"1971372758"},"language":"en","primary_location":{"id":"doi:10.1109/estimedia.2012.6507023","is_oa":false,"landing_page_url":"https://doi.org/10.1109/estimedia.2012.6507023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078340555","display_name":"Michael Milford","orcid":"https://orcid.org/0000-0002-5162-1793"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":true,"raw_author_name":"Matthew Milford","raw_affiliation_strings":["eStreams, The Institute of Electronics, Computer Science and Information Technology (ECIT), School of Electrical Engineering, Electronics and Computer Science, Queen's University Belfast"],"affiliations":[{"raw_affiliation_string":"eStreams, The Institute of Electronics, Computer Science and Information Technology (ECIT), School of Electrical Engineering, Electronics and Computer Science, Queen's University Belfast","institution_ids":["https://openalex.org/I126231945"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5036512274","display_name":"John McAllister","orcid":"https://orcid.org/0000-0002-4017-115X"},"institutions":[{"id":"https://openalex.org/I126231945","display_name":"Queen's University Belfast","ror":"https://ror.org/00hswnk62","country_code":"GB","type":"education","lineage":["https://openalex.org/I126231945"]}],"countries":["GB"],"is_corresponding":false,"raw_author_name":"John McAllister","raw_affiliation_strings":["eStreams, The Institute of Electronics, Computer Science and Information Technology (ECIT), School of Electrical Engineering, Electronics and Computer Science, Queen's University Belfast"],"affiliations":[{"raw_affiliation_string":"eStreams, The Institute of Electronics, Computer Science and Information Technology (ECIT), School of Electrical Engineering, Electronics and Computer Science, Queen's University Belfast","institution_ids":["https://openalex.org/I126231945"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5078340555"],"corresponding_institution_ids":["https://openalex.org/I126231945"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.05712736,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"12","last_page":"18"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10829","display_name":"Interconnection Networks and Systems","score":0.9987999796867371,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9987000226974487,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.8320432305335999},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.6827840209007263},{"id":"https://openalex.org/keywords/high-level-synthesis","display_name":"High-level synthesis","score":0.6335951089859009},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.5908827185630798},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5566747188568115},{"id":"https://openalex.org/keywords/memory-hierarchy","display_name":"Memory hierarchy","score":0.5300438404083252},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.5270811915397644},{"id":"https://openalex.org/keywords/sobel-operator","display_name":"Sobel operator","score":0.46302998065948486},{"id":"https://openalex.org/keywords/memory-bandwidth","display_name":"Memory bandwidth","score":0.4536738097667694},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.4523438513278961},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.4501842260360718},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4468393325805664},{"id":"https://openalex.org/keywords/exploit","display_name":"Exploit","score":0.44288378953933716},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.43848884105682373},{"id":"https://openalex.org/keywords/matrix-multiplication","display_name":"Matrix multiplication","score":0.4158499836921692},{"id":"https://openalex.org/keywords/high-memory","display_name":"High memory","score":0.4123852550983429},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3516462743282318},{"id":"https://openalex.org/keywords/image-processing","display_name":"Image processing","score":0.2061212658882141},{"id":"https://openalex.org/keywords/edge-detection","display_name":"Edge detection","score":0.19125553965568542},{"id":"https://openalex.org/keywords/image","display_name":"Image (mathematics)","score":0.1604822874069214},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.1253446340560913}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.8320432305335999},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.6827840209007263},{"id":"https://openalex.org/C58013763","wikidata":"https://www.wikidata.org/wiki/Q5754574","display_name":"High-level synthesis","level":3,"score":0.6335951089859009},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.5908827185630798},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5566747188568115},{"id":"https://openalex.org/C2778100165","wikidata":"https://www.wikidata.org/wiki/Q1589327","display_name":"Memory hierarchy","level":3,"score":0.5300438404083252},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.5270811915397644},{"id":"https://openalex.org/C30703548","wikidata":"https://www.wikidata.org/wiki/Q1757673","display_name":"Sobel operator","level":5,"score":0.46302998065948486},{"id":"https://openalex.org/C188045654","wikidata":"https://www.wikidata.org/wiki/Q17148339","display_name":"Memory bandwidth","level":2,"score":0.4536738097667694},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.4523438513278961},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.4501842260360718},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4468393325805664},{"id":"https://openalex.org/C165696696","wikidata":"https://www.wikidata.org/wiki/Q11287","display_name":"Exploit","level":2,"score":0.44288378953933716},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.43848884105682373},{"id":"https://openalex.org/C17349429","wikidata":"https://www.wikidata.org/wiki/Q1049914","display_name":"Matrix multiplication","level":3,"score":0.4158499836921692},{"id":"https://openalex.org/C2781357197","wikidata":"https://www.wikidata.org/wiki/Q5757597","display_name":"High memory","level":2,"score":0.4123852550983429},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3516462743282318},{"id":"https://openalex.org/C9417928","wikidata":"https://www.wikidata.org/wiki/Q1070689","display_name":"Image processing","level":3,"score":0.2061212658882141},{"id":"https://openalex.org/C193536780","wikidata":"https://www.wikidata.org/wiki/Q1513153","display_name":"Edge detection","level":4,"score":0.19125553965568542},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.1604822874069214},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.1253446340560913},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.0},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C115537543","wikidata":"https://www.wikidata.org/wiki/Q165596","display_name":"Cache","level":2,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C84114770","wikidata":"https://www.wikidata.org/wiki/Q46344","display_name":"Quantum","level":2,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/estimedia.2012.6507023","is_oa":false,"landing_page_url":"https://doi.org/10.1109/estimedia.2012.6507023","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE 10th Symposium on Embedded Systems for Real-time Multimedia","raw_type":"proceedings-article"},{"id":"pmh:oai:pure.qub.ac.uk/portal:publications/929d6baa-5cce-4ea1-9919-b5d1c6bf2dc6","is_oa":false,"landing_page_url":"https://pure.qub.ac.uk/en/publications/929d6baa-5cce-4ea1-9919-b5d1c6bf2dc6","pdf_url":null,"source":{"id":"https://openalex.org/S4306402319","display_name":"Research Portal (Queen's University Belfast)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I126231945","host_organization_name":"Queen's University Belfast","host_organization_lineage":["https://openalex.org/I126231945"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Milford , M &amp; McAllister , J 2012 , ' Memory-centric VDF Graph Transformations for Practical FPGA Implementation ' , Paper presented at Embedded Systems for Real-time Multimedia (ESTIMedia), 2012 IEEE 10th Symposium on , Tampere , Finland , 11/10/2012 - 12/10/2012 pp. 12-18 . https://doi.org/10.1109/ESTIMedia.2012.6507023","raw_type":"conferenceObject"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.4300000071525574,"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W115216132","https://openalex.org/W1544057354","https://openalex.org/W2005850951","https://openalex.org/W2020458826","https://openalex.org/W2024612992","https://openalex.org/W2030073746","https://openalex.org/W2081181113","https://openalex.org/W2089136983","https://openalex.org/W2119804765","https://openalex.org/W2127044011","https://openalex.org/W2141102387","https://openalex.org/W2148949838","https://openalex.org/W2165972424","https://openalex.org/W2166029537","https://openalex.org/W3141321309","https://openalex.org/W3141366627","https://openalex.org/W3146814121","https://openalex.org/W6683884178"],"related_works":["https://openalex.org/W2735130281","https://openalex.org/W1990309876","https://openalex.org/W79990711","https://openalex.org/W4295935130","https://openalex.org/W1480947737","https://openalex.org/W3010779417","https://openalex.org/W2567051523","https://openalex.org/W4236372686","https://openalex.org/W3094401657","https://openalex.org/W2976393426"],"abstract_inverted_index":{"Realising":[0],"memory":[1,17,62],"intensive":[2],"applications":[3],"such":[4,34],"as":[5],"image":[6],"and":[7,36,45,82,102,123,140,151],"video":[8],"processing":[9],"on":[10],"FPGA":[11],"requires":[12],"creation":[13],"of":[14,48,78,110,121,134,157],"complex,":[15],"multi-level":[16],"hierarchies":[18],"to":[19,31,40,53,74,90,115,132,159],"achieve":[20],"real-time":[21],"performance;":[22],"however":[23],"commerical":[24],"High":[25],"Level":[26],"Synthesis":[27],"tools":[28],"are":[29,38],"unable":[30,39],"automatically":[32],"derive":[33,59],"structures":[35,63],"hence":[37],"meet":[41],"the":[42,111,119],"demanding":[43],"bandwidth":[44],"capacity":[46],"constraints":[47],"these":[49],"applications.":[50],"Current":[51],"approaches":[52],"solving":[54],"this":[55,98,145],"problem":[56],"can":[57],"only":[58],"either":[60,72],"single-level":[61],"or":[64,76],"very":[65],"deep,":[66],"highly":[67],"inefficient":[68],"hierarchies,":[69],"leading":[70,114],"in":[71,118,148],"case":[73],"one":[75],"more":[77],"high":[79],"implementation":[80],"cost":[81,128,156],"low":[83],"performance.":[84],"This":[85],"paper":[86],"presents":[87],"an":[88,91],"enhancement":[89],"existing":[92],"MC-HLS":[93],"synthesis":[94,133],"approach":[95],"which":[96],"solves":[97],"problem;":[99],"it":[100],"exploits":[101],"eliminates":[103],"data":[104],"duplication":[105],"at":[106],"multiple":[107],"levels":[108,109,122],"generated":[112],"hierarchy,":[113],"a":[116],"reduction":[117],"number":[120],"ultimately":[124],"higher":[125],"performance,":[126],"lower":[127],"implementations.":[129],"When":[130],"applied":[131],"C-based":[135],"Motion":[136],"Estimation,":[137],"Matrix":[138],"Multiplication":[139],"Sobel":[141],"Edge":[142],"Detection":[143],"applications,":[144],"enables":[146],"reductions":[147],"Block":[149],"RAM":[150],"Look":[152],"Up":[153],"Table":[154],"(LUT)":[155],"up":[158],"25%,":[160],"whilst":[161],"simultaneously":[162],"increasing":[163],"throughput.":[164]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}
