{"id":"https://openalex.org/W4246145008","doi":"https://doi.org/10.1109/essderc53440.2021.9631798","title":"A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area","display_name":"A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area","publication_year":2021,"publication_date":"2021-09-13","ids":{"openalex":"https://openalex.org/W4246145008","doi":"https://doi.org/10.1109/essderc53440.2021.9631798"},"language":"en","primary_location":{"id":"doi:10.1109/essderc53440.2021.9631798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/essderc53440.2021.9631798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5005939302","display_name":"Peter Deaville","orcid":"https://orcid.org/0000-0001-8029-1060"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Peter Deaville","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5103156267","display_name":"Bonan Zhang","orcid":"https://orcid.org/0000-0002-7394-7022"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Bonan Zhang","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5007614100","display_name":"Lung-Yen Chen","orcid":"https://orcid.org/0000-0001-5631-5915"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Lung-Yen Chen","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101645607","display_name":"Naveen Verma","orcid":"https://orcid.org/0000-0002-8208-5030"},"institutions":[{"id":"https://openalex.org/I20089843","display_name":"Princeton University","ror":"https://ror.org/00hx57361","country_code":"US","type":"education","lineage":["https://openalex.org/I20089843"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Naveen Verma","raw_affiliation_strings":["Princeton University, Princeton, NJ, USA"],"affiliations":[{"raw_affiliation_string":"Princeton University, Princeton, NJ, USA","institution_ids":["https://openalex.org/I20089843"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5005939302"],"corresponding_institution_ids":["https://openalex.org/I20089843"],"apc_list":null,"apc_paid":null,"fwci":0.5014,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.65299352,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":91,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"75","last_page":"78"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9970999956130981,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/magnetoresistive-random-access-memory","display_name":"Magnetoresistive random-access memory","score":0.6622870564460754},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.613329291343689},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5655258297920227},{"id":"https://openalex.org/keywords/column","display_name":"Column (typography)","score":0.5606579184532166},{"id":"https://openalex.org/keywords/sensitivity","display_name":"Sensitivity (control systems)","score":0.5460366010665894},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.5253086686134338},{"id":"https://openalex.org/keywords/macro","display_name":"Macro","score":0.4861854910850525},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.48205479979515076},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4547530710697174},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4205872714519501},{"id":"https://openalex.org/keywords/in-memory-processing","display_name":"In-Memory Processing","score":0.41803738474845886},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.41296637058258057},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.3813268840312958},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3006709814071655},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2025509774684906},{"id":"https://openalex.org/keywords/search-engine","display_name":"Search engine","score":0.1374969184398651},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.13210934400558472},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08756321668624878}],"concepts":[{"id":"https://openalex.org/C46891859","wikidata":"https://www.wikidata.org/wiki/Q1061546","display_name":"Magnetoresistive random-access memory","level":3,"score":0.6622870564460754},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.613329291343689},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5655258297920227},{"id":"https://openalex.org/C2780551164","wikidata":"https://www.wikidata.org/wiki/Q2306599","display_name":"Column (typography)","level":3,"score":0.5606579184532166},{"id":"https://openalex.org/C21200559","wikidata":"https://www.wikidata.org/wiki/Q7451068","display_name":"Sensitivity (control systems)","level":2,"score":0.5460366010665894},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.5253086686134338},{"id":"https://openalex.org/C166955791","wikidata":"https://www.wikidata.org/wiki/Q629579","display_name":"Macro","level":2,"score":0.4861854910850525},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.48205479979515076},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4547530710697174},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4205872714519501},{"id":"https://openalex.org/C123593499","wikidata":"https://www.wikidata.org/wiki/Q6008583","display_name":"In-Memory Processing","level":5,"score":0.41803738474845886},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.41296637058258057},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.3813268840312958},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3006709814071655},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2025509774684906},{"id":"https://openalex.org/C97854310","wikidata":"https://www.wikidata.org/wiki/Q19541","display_name":"Search engine","level":2,"score":0.1374969184398651},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.13210934400558472},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08756321668624878},{"id":"https://openalex.org/C126042441","wikidata":"https://www.wikidata.org/wiki/Q1324888","display_name":"Frame (networking)","level":2,"score":0.0},{"id":"https://openalex.org/C23123220","wikidata":"https://www.wikidata.org/wiki/Q816826","display_name":"Information retrieval","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C164120249","wikidata":"https://www.wikidata.org/wiki/Q995982","display_name":"Web search query","level":3,"score":0.0},{"id":"https://openalex.org/C2994168587","wikidata":"https://www.wikidata.org/wiki/Q5295","display_name":"Random access memory","level":2,"score":0.0},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.0},{"id":"https://openalex.org/C194222762","wikidata":"https://www.wikidata.org/wiki/Q114486","display_name":"Query by Example","level":4,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/essderc53440.2021.9631798","is_oa":false,"landing_page_url":"https://doi.org/10.1109/essderc53440.2021.9631798","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.9100000262260437,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G3630146766","display_name":null,"funder_award_id":"FA8650-18-2-7866","funder_id":"https://openalex.org/F4320332180","funder_display_name":"Defense Advanced Research Projects Agency"}],"funders":[{"id":"https://openalex.org/F4320332180","display_name":"Defense Advanced Research Projects Agency","ror":"https://ror.org/02caytj08"},{"id":"https://openalex.org/F4320338294","display_name":"Air Force Research Laboratory","ror":"https://ror.org/02e2egq70"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W2898994846","https://openalex.org/W2933452742","https://openalex.org/W2936443718","https://openalex.org/W2974585810","https://openalex.org/W3015980402","https://openalex.org/W3015982917","https://openalex.org/W3061567197"],"related_works":["https://openalex.org/W2141626281","https://openalex.org/W2086829516","https://openalex.org/W2472395098","https://openalex.org/W1908441109","https://openalex.org/W2128922810","https://openalex.org/W1579280934","https://openalex.org/W2030816003","https://openalex.org/W4312855541","https://openalex.org/W2020463726","https://openalex.org/W3002919214"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,33,66,103,134],"first":[4],"MRAM-based":[5,109],"In-Memory-Computing":[6],"(IMC)":[7],"macro,":[8],"implemented":[9],"as":[10],"a":[11,82],"128-kb":[12],"array":[13],"in":[14,81],"an":[15],"advanced-node":[16],"22nm":[17],"FD-SOI":[18],"technology.":[19],"The":[20,100],"design":[21,101],"maximizes":[22],"IMC":[23,70,110],"row":[24],"parallelism":[25],"for":[26,108,133],"energy":[27,128],"efficiency":[28,129],"and":[29,46,59,79,127],"throughput,":[30],"while":[31,117],"addressing":[32],"critical":[34],"challenges":[35],"this":[36],"raises,":[37],"namely:":[38],"high":[39,42,105],"column":[40],"currents;":[41],"output":[43],"dynamic-range":[44],"requirements;":[45],"large":[47],"area":[48],"of":[49,65,121,130],"peripheral":[50],"readout":[51,61],"circuits.":[52],"These":[53],"are":[54,77],"addressed":[55],"through":[56],"current-insensitive":[57],"column-multiplexing":[58],"high-sensitivity":[60],"circuits,":[62],"occupying":[63],"26%":[64],"macro":[67],"area.":[68],"Residual":[69],"non-idealities,":[71],"arising":[72],"from":[73],"statistical":[74],"circuit":[75],"variations,":[76],"modeled":[78],"incorporated":[80],"chip-generalized":[83],"one-time":[84],"neural-network":[85],"training":[86],"algorithm,":[87],"with":[88],"CIFAR-10":[89],"image-classification":[90],"accuracy":[91],"demonstrated":[92],"at":[93],"90.1%,":[94],"equal":[95],"to":[96,112],"ideal":[97],"digital":[98],"computation.":[99],"addresses":[102],"particularly":[104],"sensitivity":[106],"required":[107],"compared":[111],"other":[113],"non-volatile":[114],"memory":[115],"technologies,":[116],"achieving":[118],"area-normalized":[119],"throughput":[120],"758":[122],"GOPS/mm":[123],"<sup":[124],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[125],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[126],"5.1":[131],"TOPS/w":[132],"macro.":[135]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}