{"id":"https://openalex.org/W1977212972","doi":"https://doi.org/10.1109/essderc.2012.6343381","title":"MTJ-based implication logic gates and circuit architecture for large-scale spintronic stateful logic systems","display_name":"MTJ-based implication logic gates and circuit architecture for large-scale spintronic stateful logic systems","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W1977212972","doi":"https://doi.org/10.1109/essderc.2012.6343381","mag":"1977212972"},"language":"en","primary_location":{"id":"doi:10.1109/essderc.2012.6343381","is_oa":false,"landing_page_url":"https://doi.org/10.1109/essderc.2012.6343381","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5072413078","display_name":"Hiwa Mahmoudi","orcid":"https://orcid.org/0000-0003-1467-7007"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]},{"id":"https://openalex.org/I129774422","display_name":"University of Vienna","ror":"https://ror.org/03prydq77","country_code":"AT","type":"education","lineage":["https://openalex.org/I129774422"]}],"countries":["AT"],"is_corresponding":true,"raw_author_name":"Hiwa Mahmoudi","raw_affiliation_strings":["Institute for Microelectronics, Technical University of of Vienna, Wien, Austria","Institute for Microelectronics, TU Wien, Gu\u00dfhausstra\u00dfe 27\u201329/E360, A-1040 Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Institute for Microelectronics, Technical University of of Vienna, Wien, Austria","institution_ids":["https://openalex.org/I129774422"]},{"raw_affiliation_string":"Institute for Microelectronics, TU Wien, Gu\u00dfhausstra\u00dfe 27\u201329/E360, A-1040 Wien, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5023885831","display_name":"Viktor Sverdlov","orcid":"https://orcid.org/0000-0003-1736-6976"},"institutions":[{"id":"https://openalex.org/I129774422","display_name":"University of Vienna","ror":"https://ror.org/03prydq77","country_code":"AT","type":"education","lineage":["https://openalex.org/I129774422"]},{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Viktor Sverdlov","raw_affiliation_strings":["Institute for Microelectronics, Technical University of of Vienna, Wien, Austria","Institute for Microelectronics, TU Wien, Gu\u00dfhausstra\u00dfe 27\u201329/E360, A-1040 Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Institute for Microelectronics, Technical University of of Vienna, Wien, Austria","institution_ids":["https://openalex.org/I129774422"]},{"raw_affiliation_string":"Institute for Microelectronics, TU Wien, Gu\u00dfhausstra\u00dfe 27\u201329/E360, A-1040 Wien, Austria","institution_ids":["https://openalex.org/I145847075"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5043510129","display_name":"S. Selberherr","orcid":"https://orcid.org/0000-0002-5583-6177"},"institutions":[{"id":"https://openalex.org/I145847075","display_name":"TU Wien","ror":"https://ror.org/04d836q62","country_code":"AT","type":"education","lineage":["https://openalex.org/I145847075"]},{"id":"https://openalex.org/I129774422","display_name":"University of Vienna","ror":"https://ror.org/03prydq77","country_code":"AT","type":"education","lineage":["https://openalex.org/I129774422"]}],"countries":["AT"],"is_corresponding":false,"raw_author_name":"Siegfried Selberherr","raw_affiliation_strings":["Institute for Microelectronics, Technical University of of Vienna, Wien, Austria","Institute for Microelectronics, TU Wien, Gu\u00dfhausstra\u00dfe 27\u201329/E360, A-1040 Wien, Austria"],"affiliations":[{"raw_affiliation_string":"Institute for Microelectronics, Technical University of of Vienna, Wien, Austria","institution_ids":["https://openalex.org/I129774422"]},{"raw_affiliation_string":"Institute for Microelectronics, TU Wien, Gu\u00dfhausstra\u00dfe 27\u201329/E360, A-1040 Wien, Austria","institution_ids":["https://openalex.org/I145847075"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5072413078"],"corresponding_institution_ids":["https://openalex.org/I129774422","https://openalex.org/I145847075"],"apc_list":null,"apc_paid":null,"fwci":0.982,"has_fulltext":false,"cited_by_count":9,"citation_normalized_percentile":{"value":0.77086429,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":"57","issue":null,"first_page":"254","last_page":"257"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.630740225315094},{"id":"https://openalex.org/keywords/stateful-firewall","display_name":"Stateful firewall","score":0.626266598701477},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5923412442207336},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5460708737373352},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5458997488021851},{"id":"https://openalex.org/keywords/resistor\u2013transistor-logic","display_name":"Resistor\u2013transistor logic","score":0.4675148129463196},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.4413607120513916},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.4205417335033417},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3465309143066406},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2972179055213928},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.28398770093917847},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.28244510293006897},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.16965991258621216},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09945645928382874}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.630740225315094},{"id":"https://openalex.org/C22927095","wikidata":"https://www.wikidata.org/wiki/Q1784206","display_name":"Stateful firewall","level":3,"score":0.626266598701477},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5923412442207336},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5460708737373352},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5458997488021851},{"id":"https://openalex.org/C180405849","wikidata":"https://www.wikidata.org/wiki/Q173464","display_name":"Resistor\u2013transistor logic","level":5,"score":0.4675148129463196},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.4413607120513916},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.4205417335033417},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3465309143066406},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2972179055213928},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.28398770093917847},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.28244510293006897},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.16965991258621216},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09945645928382874},{"id":"https://openalex.org/C158379750","wikidata":"https://www.wikidata.org/wiki/Q214111","display_name":"Network packet","level":2,"score":0.0},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/essderc.2012.6343381","is_oa":false,"landing_page_url":"https://doi.org/10.1109/essderc.2012.6343381","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":22,"referenced_works":["https://openalex.org/W1964504828","https://openalex.org/W1965245884","https://openalex.org/W1996731722","https://openalex.org/W2001809292","https://openalex.org/W2003671162","https://openalex.org/W2004640050","https://openalex.org/W2014987330","https://openalex.org/W2025173691","https://openalex.org/W2025674646","https://openalex.org/W2060676233","https://openalex.org/W2088797290","https://openalex.org/W2105401464","https://openalex.org/W2106223839","https://openalex.org/W2110134128","https://openalex.org/W2112181056","https://openalex.org/W2116344741","https://openalex.org/W2147570207","https://openalex.org/W2149623497","https://openalex.org/W2542473330","https://openalex.org/W2543205889","https://openalex.org/W3146874818","https://openalex.org/W6677325608"],"related_works":["https://openalex.org/W2789662562","https://openalex.org/W4214735176","https://openalex.org/W2082591327","https://openalex.org/W2167525841","https://openalex.org/W4390345136","https://openalex.org/W2601542976","https://openalex.org/W1504140885","https://openalex.org/W2001164331","https://openalex.org/W4367312965","https://openalex.org/W3166523576"],"abstract_inverted_index":{"Because":[0],"of":[1,13,86,92],"the":[2,40,46,53,84,87,93,109],"easy":[3],"integration":[4],"with":[5,119],"CMOS,":[6],"non-volatility,":[7],"reconfiguration":[8],"capability,":[9],"and":[10,21,27,33,107],"fast-switching":[11],"speed":[12],"magnetic":[14],"tunnel":[15],"junctions":[16],"(MTJs),":[17],"this":[18],"work":[19],"proposes":[20],"investigates":[22],"stateful":[23,95],"IMP-based":[24],"logic":[25,38,57,70,96,114],"gates":[26,71],"circuit":[28],"architecture":[29],"for":[30,78,111],"future":[31],"reconfigurable":[32],"nonvolatile":[34,99],"computing":[35,48,105],"systems.":[36],"Stateful":[37],"uses":[39],"memory":[41,102],"unit":[42],"(MTJ":[43],"device)":[44],"as":[45],"main":[47],"element":[49],"(logic":[50],"gate)":[51],"unlike":[52],"previously":[54],"proposed":[55],"MTJ-based":[56,120],"circuits,":[58],"where":[59],"MTJs":[60,81],"are":[61,72],"only":[62],"ancillary":[63],"devices":[64],"in":[65],"logical":[66,104],"computations.":[67],"Spintronic":[68],"IMP":[69,88],"analyzed":[73],"using":[74],"a":[75],"SPICE":[76],"model":[77],"spin-transfer":[79],"torque":[80],"to":[82,103,116],"demonstrate":[83],"reliability":[85],"operation.":[89],"The":[90],"realization":[91],"spintronic":[94],"operations":[97],"extends":[98],"electronics":[100],"from":[101],"applications":[106],"opens":[108],"door":[110],"more":[112],"complex":[113],"functions":[115],"be":[117],"realized":[118],"devices.":[121]},"counts_by_year":[{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":3}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}