{"id":"https://openalex.org/W4387411259","doi":"https://doi.org/10.1109/esscirc59616.2023.10268737","title":"A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path","display_name":"A Fully Synthesizable DPLL with Background Gain Mismatch Calibrated Feedforward Phase Noise Cancellation Path","publication_year":2023,"publication_date":"2023-09-11","ids":{"openalex":"https://openalex.org/W4387411259","doi":"https://doi.org/10.1109/esscirc59616.2023.10268737"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc59616.2023.10268737","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc59616.2023.10268737","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5060789782","display_name":"Waleed Madany","orcid":"https://orcid.org/0000-0002-5653-9983"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Waleed Madany","raw_affiliation_strings":["Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5040477650","display_name":"Yuncheng Zhang","orcid":"https://orcid.org/0000-0001-6467-3667"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yuncheng Zhang","raw_affiliation_strings":["Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042366511","display_name":"Ashbir Aviat Fadila","orcid":"https://orcid.org/0000-0002-5529-8217"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Ashbir Aviat Fadila","raw_affiliation_strings":["Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081527973","display_name":"H\u00f3ngy\u00e8 Hu\u00e1ng","orcid":"https://orcid.org/0000-0001-6071-2075"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hongye Huang","raw_affiliation_strings":["Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068137637","display_name":"Junjun Qiu","orcid":"https://orcid.org/0000-0002-3698-4369"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Junjun Qiu","raw_affiliation_strings":["Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028333708","display_name":"Atsushi Shirane","orcid":"https://orcid.org/0000-0001-8172-4323"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsushi Shirane","raw_affiliation_strings":["Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552","institution_ids":["https://openalex.org/I114531698"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5064086312","display_name":"Kenichi Okada","orcid":"https://orcid.org/0000-0002-1082-7672"},"institutions":[{"id":"https://openalex.org/I114531698","display_name":"Tokyo Institute of Technology","ror":"https://ror.org/0112mx960","country_code":"JP","type":"education","lineage":["https://openalex.org/I114531698"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenichi Okada","raw_affiliation_strings":["Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552"],"affiliations":[{"raw_affiliation_string":"Tokyo Institute of Technology 2-12-1-S3-28, Ookayama,Department of Electrical and Electronic Engineering,Meguro-ku,Tokyo,Japan,152-8552","institution_ids":["https://openalex.org/I114531698"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5060789782"],"corresponding_institution_ids":["https://openalex.org/I114531698"],"apc_list":null,"apc_paid":null,"fwci":1.0395,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.76703894,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"265","last_page":"268"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/dpll-algorithm","display_name":"DPLL algorithm","score":0.8664405345916748},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8541847467422485},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.596876323223114},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.5605834126472473},{"id":"https://openalex.org/keywords/feed-forward","display_name":"Feed forward","score":0.5441151857376099},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5101428627967834},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.4982287883758545},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.4974718391895294},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.4368080794811249},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.43605464696884155},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4345557391643524},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3481266498565674},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.3239939212799072},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.26031142473220825},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25919580459594727},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.20892804861068726}],"concepts":[{"id":"https://openalex.org/C143936061","wikidata":"https://www.wikidata.org/wiki/Q2030088","display_name":"DPLL algorithm","level":4,"score":0.8664405345916748},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8541847467422485},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.596876323223114},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.5605834126472473},{"id":"https://openalex.org/C38858127","wikidata":"https://www.wikidata.org/wiki/Q5441228","display_name":"Feed forward","level":2,"score":0.5441151857376099},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5101428627967834},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.4982287883758545},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.4974718391895294},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.4368080794811249},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.43605464696884155},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4345557391643524},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3481266498565674},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.3239939212799072},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.26031142473220825},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25919580459594727},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.20892804861068726},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/esscirc59616.2023.10268737","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc59616.2023.10268737","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},{"id":"pmh:oai:irdb.nii.ac.jp:00897:0006394601","is_oa":false,"landing_page_url":"http://t2r2.star.titech.ac.jp/cgi-bin/publicationinfo.cgi?q_publication_content_number=CTT100918101","pdf_url":null,"source":{"id":"https://openalex.org/S7407056385","display_name":"Institutional Repositories DataBase (IRDB)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I184597095","host_organization_name":"National Institute of Informatics","host_organization_lineage":["https://openalex.org/I184597095"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":null,"raw_type":"conference paper"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8999999761581421,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1965272013","https://openalex.org/W2147533202","https://openalex.org/W2790703790","https://openalex.org/W2801898480","https://openalex.org/W2952154040","https://openalex.org/W3003987747","https://openalex.org/W3015726451","https://openalex.org/W3048794339","https://openalex.org/W3085612199","https://openalex.org/W3099426297","https://openalex.org/W4280580466","https://openalex.org/W6681793391"],"related_works":["https://openalex.org/W1488060887","https://openalex.org/W2380467267","https://openalex.org/W1980525453","https://openalex.org/W2325206724","https://openalex.org/W2059960378","https://openalex.org/W2043945969","https://openalex.org/W4390099038","https://openalex.org/W2103754166","https://openalex.org/W2139484866","https://openalex.org/W2058003010"],"abstract_inverted_index":{"This":[0],"work":[1],"presents":[2],"a":[3,8,38,77],"fully":[4],"synthesizable":[5],"DPLL":[6,54],"with":[7,60],"feedforward":[9],"phase":[10],"noise":[11],"cancellation":[12],"(FPNC)":[13],"path.":[14],"The":[15,74],"gain":[16],"mismatch":[17],"between":[18],"the":[19,28,40,44,53,91],"FPNC":[20],"path":[21],"components":[22],"has":[23],"been":[24],"calibrated":[25],"digitally":[26],"in":[27,70],"background":[29],"against":[30],"process,":[31],"voltage,":[32],"and":[33,99,115],"temperature":[34],"(PVT)":[35],"variations.":[36],"As":[37],"result,":[39],"rms":[41],"value":[42],"of":[43,63,93],"absolute":[45],"jitter":[46,78],"was":[47,68],"reduced":[48],"over":[49],"different":[50,112],"conditions":[51],"beyond":[52],"stability":[55],"barrier.":[56],"A":[57],"prototype":[58],"chip":[59],"an":[61],"area":[62],"0.105mm":[64],"<sup":[65],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[66],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[67],"fabricated":[69],"65nm":[71],"CMOS":[72],"technology.":[73],"measurements":[75],"showed":[76],"reduction":[79],"at":[80,90],"1.":[81,86],"0GHz":[82],"output":[83,116],"frequency":[84],"from":[85,102],"0ps":[87],"to":[88,104],"753fs":[89],"cost":[92],"0.":[94],"7mW":[95],"extra":[96],"power":[97],"consumption":[98],"FoM":[100],"improvement":[101],"-234.4dB":[103],"-236dB.":[105],"Also,":[106],"similar":[107],"improvements":[108],"were":[109],"measured":[110],"under":[111],"voltages,":[113],"chips,":[114],"frequencies.":[117]},"counts_by_year":[{"year":2025,"cited_by_count":5},{"year":2024,"cited_by_count":3}],"updated_date":"2026-04-04T16:13:02.066488","created_date":"2025-10-10T00:00:00"}