{"id":"https://openalex.org/W4308089772","doi":"https://doi.org/10.1109/esscirc55480.2022.9911462","title":"A Full D-band Multi-Gbit RF-DAC in 90 nm SiGe BiCMOS based on Passive Vector Aggregation","display_name":"A Full D-band Multi-Gbit RF-DAC in 90 nm SiGe BiCMOS based on Passive Vector Aggregation","publication_year":2022,"publication_date":"2022-09-19","ids":{"openalex":"https://openalex.org/W4308089772","doi":"https://doi.org/10.1109/esscirc55480.2022.9911462"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc55480.2022.9911462","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc55480.2022.9911462","pdf_url":null,"source":{"id":"https://openalex.org/S4363608323","display_name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5079599454","display_name":"Tim Maiwald","orcid":"https://orcid.org/0000-0002-5036-8490"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Tim Maiwald","raw_affiliation_strings":["Institute for Electronics Engineering, Friedrich-Alexander-University Erlangen-N&#x00FC;rnberg,Erlangen,Germany,91058"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Electronics Engineering, Friedrich-Alexander-University Erlangen-N&#x00FC;rnberg,Erlangen,Germany,91058","institution_ids":["https://openalex.org/I181369854"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048571765","display_name":"Akshay Visweswaran","orcid":"https://orcid.org/0000-0002-1984-919X"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Akshay Visweswaran","raw_affiliation_strings":["Imec,Leuven,Belgium,B-3001"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Imec,Leuven,Belgium,B-3001","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5060917100","display_name":"Klaus Aufinger","orcid":"https://orcid.org/0000-0002-7884-7987"},"institutions":[{"id":"https://openalex.org/I137594350","display_name":"Infineon Technologies (Germany)","ror":"https://ror.org/005kw6t15","country_code":"DE","type":"company","lineage":["https://openalex.org/I137594350"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Klaus Aufinger","raw_affiliation_strings":["Infineon Technologies AG,Neubiberg,Germany","Infineon Technologies AG, Neubiberg, Germany"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Infineon Technologies AG,Neubiberg,Germany","institution_ids":["https://openalex.org/I137594350"]},{"raw_affiliation_string":"Infineon Technologies AG, Neubiberg, Germany","institution_ids":["https://openalex.org/I137594350"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5102944273","display_name":"Robert Weigel","orcid":"https://orcid.org/0000-0002-2919-9522"},"institutions":[{"id":"https://openalex.org/I181369854","display_name":"Friedrich-Alexander-Universit\u00e4t Erlangen-N\u00fcrnberg","ror":"https://ror.org/00f7hpc57","country_code":"DE","type":"education","lineage":["https://openalex.org/I181369854"]}],"countries":["DE"],"is_corresponding":false,"raw_author_name":"Robert Weigel","raw_affiliation_strings":["Institute for Electronics Engineering, Friedrich-Alexander-University Erlangen-N&#x00FC;rnberg,Erlangen,Germany,91058"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Institute for Electronics Engineering, Friedrich-Alexander-University Erlangen-N&#x00FC;rnberg,Erlangen,Germany,91058","institution_ids":["https://openalex.org/I181369854"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.3189,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.42362811,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"54","issue":null,"first_page":"449","last_page":"452"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.998199999332428,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10262","display_name":"Microwave Engineering and Waveguides","score":0.9976999759674072,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/bicmos","display_name":"BiCMOS","score":0.7075477838516235},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5662862658500671},{"id":"https://openalex.org/keywords/phase-shift-keying","display_name":"Phase-shift keying","score":0.5564386248588562},{"id":"https://openalex.org/keywords/modulation","display_name":"Modulation (music)","score":0.5373420119285583},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5134068727493286},{"id":"https://openalex.org/keywords/balun","display_name":"Balun","score":0.5132343769073486},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.481610506772995},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.47151386737823486},{"id":"https://openalex.org/keywords/quadrature-amplitude-modulation","display_name":"Quadrature amplitude modulation","score":0.46527737379074097},{"id":"https://openalex.org/keywords/radio-frequency","display_name":"Radio frequency","score":0.4404981732368469},{"id":"https://openalex.org/keywords/baseband","display_name":"Baseband","score":0.43834561109542847},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3954227864742279},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3235393464565277},{"id":"https://openalex.org/keywords/antenna","display_name":"Antenna (radio)","score":0.2690567672252655},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.23375675082206726},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.19898191094398499},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.17268449068069458},{"id":"https://openalex.org/keywords/bit-error-rate","display_name":"Bit error rate","score":0.14894387125968933}],"concepts":[{"id":"https://openalex.org/C62427370","wikidata":"https://www.wikidata.org/wiki/Q173416","display_name":"BiCMOS","level":4,"score":0.7075477838516235},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5662862658500671},{"id":"https://openalex.org/C186378180","wikidata":"https://www.wikidata.org/wiki/Q4874866","display_name":"Phase-shift keying","level":4,"score":0.5564386248588562},{"id":"https://openalex.org/C123079801","wikidata":"https://www.wikidata.org/wiki/Q750240","display_name":"Modulation (music)","level":2,"score":0.5373420119285583},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5134068727493286},{"id":"https://openalex.org/C114489654","wikidata":"https://www.wikidata.org/wiki/Q805838","display_name":"Balun","level":3,"score":0.5132343769073486},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.481610506772995},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.47151386737823486},{"id":"https://openalex.org/C32409245","wikidata":"https://www.wikidata.org/wiki/Q749753","display_name":"Quadrature amplitude modulation","level":4,"score":0.46527737379074097},{"id":"https://openalex.org/C74064498","wikidata":"https://www.wikidata.org/wiki/Q3396184","display_name":"Radio frequency","level":2,"score":0.4404981732368469},{"id":"https://openalex.org/C65165936","wikidata":"https://www.wikidata.org/wiki/Q575784","display_name":"Baseband","level":3,"score":0.43834561109542847},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3954227864742279},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3235393464565277},{"id":"https://openalex.org/C21822782","wikidata":"https://www.wikidata.org/wiki/Q131214","display_name":"Antenna (radio)","level":2,"score":0.2690567672252655},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.23375675082206726},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.19898191094398499},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.17268449068069458},{"id":"https://openalex.org/C56296756","wikidata":"https://www.wikidata.org/wiki/Q840922","display_name":"Bit error rate","level":3,"score":0.14894387125968933},{"id":"https://openalex.org/C127162648","wikidata":"https://www.wikidata.org/wiki/Q16858953","display_name":"Channel (broadcasting)","level":2,"score":0.0},{"id":"https://openalex.org/C24890656","wikidata":"https://www.wikidata.org/wiki/Q82811","display_name":"Acoustics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc55480.2022.9911462","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc55480.2022.9911462","pdf_url":null,"source":{"id":"https://openalex.org/S4363608323","display_name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.5400000214576721,"id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G423422435","display_name":null,"funder_award_id":"16ESE0214","funder_id":"https://openalex.org/F4320321114","funder_display_name":"Bundesministerium f\u00fcr Bildung und Forschung"},{"id":"https://openalex.org/G6680017216","display_name":null,"funder_award_id":"ESCS16104","funder_id":"https://openalex.org/F4320320300","funder_display_name":"European Commission"}],"funders":[{"id":"https://openalex.org/F4320320300","display_name":"European Commission","ror":"https://ror.org/00k4n6c32"},{"id":"https://openalex.org/F4320321114","display_name":"Bundesministerium f\u00fcr Bildung und Forschung","ror":"https://ror.org/04pz7b180"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W2555469335","https://openalex.org/W2592683973","https://openalex.org/W2970628702","https://openalex.org/W3130418500","https://openalex.org/W3161871591","https://openalex.org/W4220787334"],"related_works":["https://openalex.org/W2548689985","https://openalex.org/W2385753426","https://openalex.org/W2893995248","https://openalex.org/W2148868771","https://openalex.org/W2085207364","https://openalex.org/W2173645393","https://openalex.org/W2901356766","https://openalex.org/W2079101534","https://openalex.org/W2018164385","https://openalex.org/W1993069619"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"the":[3,19,27,96,143,155,162],"first":[4],"fully":[5],"integrated":[6],"RF-DAC":[7,28],"for":[8,14,59],"realizing":[9],"and":[10,48,77,89,184],"passively":[11],"scaling":[12,63],"QPSK-signals":[13],"generating":[15],"higher-order":[16],"modulations":[17],"over":[18,142],"entire":[20,144],"D-band":[21],"(110\u2013170":[22],"GHz).":[23],"Vector-symbol":[24],"generation":[25],"in":[26,122],"is":[29,46,67,92,158],"accomplished":[30,69],"via":[31],"compact":[32],"distributed":[33],"passives":[34],"on":[35,82,118],"chip.":[36],"In":[37],"this":[38],"modulator":[39],"architecture,":[40],"a":[41,51,60,71,78,131,137,148,180],"sinusoidal":[42],"local-oscillator":[43],"(LO)":[44],"signal":[45],"split":[47],"weighted":[49],"by":[50,105,161],"backward-wave":[52],"directional":[53],"coupler":[54],"to":[55],"meet":[56],"length":[57],"requirements":[58],"complex-valued":[61],"RF-signal":[62],"vector.":[64],"QPSK":[65,111],"vector-modulation":[66],"then":[68],"with":[70,95,136],"Lange":[72],"Coupler,":[73],"two":[74],"Marchand":[75],"baluns":[76],"switch":[79],"octet":[80],"operating":[81],"four":[83],"LO":[84],"phases":[85],"(0\u00b0,":[86],"90\u00b0,":[87],"180\u00b0":[88],"270\u00b0),":[90],"which":[91],"driven":[93],"directly":[94],"data":[97],"streams.":[98],"Higher-order":[99],"modulation":[100],"schemes":[101],"are":[102],"subsequently":[103],"created":[104],"summing":[106],"RF":[107],"outputs":[108],"of":[109,133,140,151,191],"individual":[110],"unit":[112],"cells.":[113],"A":[114],"16-QAM":[115],"modulator,":[116],"based":[117],"two-way":[119],"summing,":[120],"prototyped":[121],"Infineon's":[123],"advanced":[124],"90":[125],"nm":[126],"SiGe":[127],"BiCMOS":[128],"technology":[129],"demonstrating":[130],"datarate":[132,150,157],"6.4":[134],"Gbps":[135],"measured":[138,156],"EVM":[139],"<8%":[141],"D-band.":[145],"Simulations":[146],"show":[147],"maximum":[149],"60":[152],"Gbps,":[153],"however,":[154],"currently":[159],"limited":[160],"test":[163],"setup":[164],"comprising":[165],"an":[166],"in-house":[167],"low-cost":[168],"FPGA":[169],"clocked":[170],"at":[171],"1.6":[172],"GHz.":[173],"The":[174],"chip":[175],"consumes":[176],"120":[177],"mW":[178],"from":[179],"2.1":[181],"V":[182],"supply":[183],"occupies":[185],"0.36":[186],"mm":[187],"<sup":[188],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[189],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[190],"core":[192],"area.":[193]},"counts_by_year":[{"year":2023,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}