{"id":"https://openalex.org/W4308089875","doi":"https://doi.org/10.1109/esscirc55480.2022.9911315","title":"An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering","display_name":"An Inductorless Fractional-N PLL Using Harmonic-Mixer-Based Dual Feedback and High-OSR Delta-Sigma-Modulator with Phase-Domain Filtering","publication_year":2022,"publication_date":"2022-09-19","ids":{"openalex":"https://openalex.org/W4308089875","doi":"https://doi.org/10.1109/esscirc55480.2022.9911315"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc55480.2022.9911315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc55480.2022.9911315","pdf_url":null,"source":{"id":"https://openalex.org/S4363608323","display_name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5001698880","display_name":"Masaru Osada","orcid":"https://orcid.org/0000-0002-2551-4863"},"institutions":[{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":true,"raw_author_name":"Masaru Osada","raw_affiliation_strings":["The University of Tokyo,Department of Electrical Engineering and Information Systems,Tokyo,Japan","Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"The University of Tokyo,Department of Electrical Engineering and Information Systems,Tokyo,Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]},{"raw_affiliation_string":"Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5047294489","display_name":"Zule Xu","orcid":"https://orcid.org/0000-0001-6899-3860"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Zule Xu","raw_affiliation_strings":["Systems Design Lab, School of Engineering, The University of Tokyo,Tokyo,Japan","Systems Design Lab, School of Engineering, The University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"Systems Design Lab, School of Engineering, The University of Tokyo,Tokyo,Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Systems Design Lab, School of Engineering, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007028121","display_name":"Tetsuya Iizuka","orcid":"https://orcid.org/0000-0002-1512-4714"},"institutions":[{"id":"https://openalex.org/I14396692","display_name":"Tokyo University of Information Sciences","ror":"https://ror.org/044bdx604","country_code":"JP","type":"education","lineage":["https://openalex.org/I14396692"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tetsuya Iizuka","raw_affiliation_strings":["The University of Tokyo,Department of Electrical Engineering and Information Systems,Tokyo,Japan","Systems Design Lab, School of Engineering, The University of Tokyo, Tokyo, Japan","Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan"],"affiliations":[{"raw_affiliation_string":"The University of Tokyo,Department of Electrical Engineering and Information Systems,Tokyo,Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]},{"raw_affiliation_string":"Systems Design Lab, School of Engineering, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]},{"raw_affiliation_string":"Department of Electrical Engineering and Information Systems, The University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5001698880"],"corresponding_institution_ids":["https://openalex.org/I14396692","https://openalex.org/I74801974"],"apc_list":null,"apc_paid":null,"fwci":1.2889,"has_fulltext":false,"cited_by_count":4,"citation_normalized_percentile":{"value":0.78018667,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"245","last_page":"248"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9952999949455261,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8464109301567078},{"id":"https://openalex.org/keywords/delta-sigma-modulation","display_name":"Delta-sigma modulation","score":0.6883538365364075},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.6591853499412537},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6069435477256775},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5749784708023071},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.47182661294937134},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.45219218730926514},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.43132102489471436},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3691336214542389},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25419551134109497},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.13894623517990112}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8464109301567078},{"id":"https://openalex.org/C68754193","wikidata":"https://www.wikidata.org/wiki/Q1184820","display_name":"Delta-sigma modulation","level":3,"score":0.6883538365364075},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.6591853499412537},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6069435477256775},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5749784708023071},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.47182661294937134},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.45219218730926514},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.43132102489471436},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3691336214542389},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25419551134109497},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.13894623517990112}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc55480.2022.9911315","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc55480.2022.9911315","pdf_url":null,"source":{"id":"https://openalex.org/S4363608323","display_name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"conference"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7799999713897705,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[{"id":"https://openalex.org/G1833149672","display_name":null,"funder_award_id":"JP20K14786","funder_id":"https://openalex.org/F4320322832","funder_display_name":"University of Tokyo"}],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"}],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1948778041","https://openalex.org/W2008386962","https://openalex.org/W2517568888","https://openalex.org/W2884049905","https://openalex.org/W2920923622","https://openalex.org/W2984668191","https://openalex.org/W3048378545","https://openalex.org/W3100848204","https://openalex.org/W3134323708","https://openalex.org/W3134627429","https://openalex.org/W3185156126","https://openalex.org/W4220803856"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W2104055211","https://openalex.org/W2498262093","https://openalex.org/W2474043983","https://openalex.org/W2544336511","https://openalex.org/W2566880546","https://openalex.org/W2078513307","https://openalex.org/W1978186604","https://openalex.org/W2144737022","https://openalex.org/W2124954209"],"abstract_inverted_index":{"An":[0],"inductorless":[1],"Harmonic-Mixer":[2],"(HM)":[3],"based":[4],"fractional-N":[5],"PLL":[6],"is":[7],"proposed.":[8],"It":[9],"simultaneously":[10],"achieves":[11,44],"Delta-Sigma-Modulator":[12],"(DSM)":[13],"noise":[14],"suppression":[15],"and":[16,26,57],"a":[17,23,45,59],"wide":[18],"loop":[19],"bandwidth":[20],"by":[21],"employing":[22],"high-OSR":[24],"DSM":[25],"nested-PLL-based":[27],"phase-domain":[28],"lowpass":[29],"filtering":[30],"inside":[31],"of":[32],"the":[33],"dual-feedback":[34],"architecture.":[35],"A":[36],"2.8-3.5":[37],"GHz":[38],"prototype":[39],"implemented":[40],"in":[41],"65-nm":[42],"CMOS":[43],"-227.6dB":[46],"FoM":[47],"with":[48,53,58],"an":[49],"8":[50],"MHz":[51],"bandwidth,":[52],"no":[54,63],"calibration":[55],"circuitry":[56],"compact":[60],"layout":[61],"containing":[62],"inductors.":[64]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}