{"id":"https://openalex.org/W3210252004","doi":"https://doi.org/10.1109/esscirc53450.2021.9567783","title":"Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates","display_name":"Dual-Input Pseudo-CMOS Logic for Digital Applications on Flexible Substrates","publication_year":2021,"publication_date":"2021-09-13","ids":{"openalex":"https://openalex.org/W3210252004","doi":"https://doi.org/10.1109/esscirc53450.2021.9567783","mag":"3210252004"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc53450.2021.9567783","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc53450.2021.9567783","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"https://zenodo.org/record/6344855","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5009436791","display_name":"Hikmet \u00c7eliker","orcid":"https://orcid.org/0000-0001-8429-0153"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]},{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Hikmet Celiker","raw_affiliation_strings":["KU Leuven, Leuven, Belgium","imec, Heverlee, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KU Leuven, Leuven, Belgium","institution_ids":["https://openalex.org/I99464096"]},{"raw_affiliation_string":"imec, Heverlee, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076274517","display_name":"Wim Dehaene","orcid":"https://orcid.org/0000-0002-6792-7965"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]},{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Wim Dehaene","raw_affiliation_strings":["KU Leuven, Leuven, Belgium","imec, Heverlee, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KU Leuven, Leuven, Belgium","institution_ids":["https://openalex.org/I99464096"]},{"raw_affiliation_string":"imec, Heverlee, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5044710002","display_name":"Kris Myny","orcid":"https://orcid.org/0000-0002-5230-495X"},"institutions":[{"id":"https://openalex.org/I4210114974","display_name":"IMEC","ror":"https://ror.org/02kcbn207","country_code":"BE","type":"nonprofit","lineage":["https://openalex.org/I4210114974"]},{"id":"https://openalex.org/I99464096","display_name":"KU Leuven","ror":"https://ror.org/05f950310","country_code":"BE","type":"education","lineage":["https://openalex.org/I99464096"]}],"countries":["BE"],"is_corresponding":false,"raw_author_name":"Kris Myny","raw_affiliation_strings":["KU Leuven, Leuven, Belgium","imec, Heverlee, Belgium"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"KU Leuven, Leuven, Belgium","institution_ids":["https://openalex.org/I99464096"]},{"raw_affiliation_string":"imec, Heverlee, Belgium","institution_ids":["https://openalex.org/I4210114974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":2.0349,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":{"value":0.86868928,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"255","last_page":"258"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10623","display_name":"Thin-Film Transistor Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10623","display_name":"Thin-Film Transistor Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11272","display_name":"Nanowire Synthesis and Applications","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7150267362594604},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.6558908820152283},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6425034403800964},{"id":"https://openalex.org/keywords/and-or-invert","display_name":"AND-OR-Invert","score":0.5989730358123779},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5724909901618958},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5343360900878906},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5229150056838989},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4789224863052368},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.46944141387939453},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.4533029794692993},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.421022891998291},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.3677825927734375},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2816716134548187},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21787428855895996}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7150267362594604},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.6558908820152283},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6425034403800964},{"id":"https://openalex.org/C130126468","wikidata":"https://www.wikidata.org/wiki/Q4652943","display_name":"AND-OR-Invert","level":5,"score":0.5989730358123779},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5724909901618958},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5343360900878906},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5229150056838989},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4789224863052368},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.46944141387939453},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.4533029794692993},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.421022891998291},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.3677825927734375},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2816716134548187},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21787428855895996}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/esscirc53450.2021.9567783","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc53450.2021.9567783","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},{"id":"pmh:oai:zenodo.org:6344855","is_oa":true,"landing_page_url":"https://zenodo.org/record/6344855","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferencePaper"}],"best_oa_location":{"id":"pmh:oai:zenodo.org:6344855","is_oa":true,"landing_page_url":"https://zenodo.org/record/6344855","pdf_url":null,"source":{"id":"https://openalex.org/S4306400562","display_name":"Zenodo (CERN European Organization for Nuclear Research)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I67311998","host_organization_name":"European Organization for Nuclear Research","host_organization_lineage":["https://openalex.org/I67311998"],"host_organization_lineage_names":[],"type":"repository"},"license":"cc-by","license_id":"https://openalex.org/licenses/cc-by","version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferencePaper"},"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W2069389000","https://openalex.org/W2592850638","https://openalex.org/W2626758433","https://openalex.org/W2890340907","https://openalex.org/W2945941455","https://openalex.org/W2947266953","https://openalex.org/W2973569033","https://openalex.org/W3037795088","https://openalex.org/W3087928436","https://openalex.org/W6734005261","https://openalex.org/W6739895025"],"related_works":["https://openalex.org/W2098419840","https://openalex.org/W1827076955","https://openalex.org/W1977171228","https://openalex.org/W2121963733","https://openalex.org/W1985308002","https://openalex.org/W2170504327","https://openalex.org/W2542337934","https://openalex.org/W1702497178","https://openalex.org/W2142914495","https://openalex.org/W1990901299"],"abstract_inverted_index":{"A":[0],"new":[1],"standard":[2],"cell":[3],"topology,":[4],"Dual-Input":[5],"Pseudo-CMOS":[6,30],"(DIPC),":[7],"for":[8,80,153],"dual-gate":[9],"Indium-Gallium-Zinc-Oxide":[10],"(IGZO)":[11],"thin-film":[12],"transistor":[13,60],"(TFT)":[14],"technology":[15],"on":[16],"flexible":[17],"substrates":[18],"is":[19,25],"presented.":[20],"The":[21,102],"proposed":[22,103,150],"logic":[23,67,159],"topology":[24,104,152],"compared":[26],"with":[27,83,95],"the":[28,48,62,71,74,108,115,139,149],"conventional":[29],"in":[31,66],"terms":[32],"of":[33,50,64,99,110,121,131,141],"robustness":[34],"(noise":[35],"margin),":[36],"speed":[37,72],"performance,":[38],"power":[39,122],"consumption":[40],"and":[41,73,89,114,128,161],"area":[42],"usage.":[43],"This":[44,134],"work":[45,135],"shows":[46],"that":[47,138],"back-gate":[49],"a":[51,57,96],"TFT":[52],"can":[53,143],"be":[54,144],"used":[55],"as":[56,157],"separate":[58],"parallel":[59],"reducing":[61],"number":[63,109,140],"devices":[65],"gates":[68],"without":[69],"compromising":[70],"power.":[75],"Two":[76],"32-bit":[77],"code":[78],"generators":[79],"RFID":[81],"transponders":[82],"both":[84],"libraries":[85],"have":[86],"been":[87],"designed":[88],"fabricated":[90],"using":[91,148],"n-type":[92],"only":[93,118],"TFTs":[94,111,142],"channel":[97],"length":[98],"5":[100],"\u00b5m.":[101],"allowed":[105],"to":[106],"reduce":[107],"by":[112,147],"24%":[113],"chip":[116],"consumes":[117],"2.2":[119],"\u00b5W":[120],"at":[123],"4":[124],"kHz":[125],"clock":[126],"frequency":[127],"1":[129],"V":[130],"supply":[132],"voltage.":[133],"also":[136],"forecasts":[137],"reduced":[145],"strongly":[146],"DIPC":[151],"complex":[154],"designs":[155],"such":[156],"arithmetic":[158],"units":[160],"microprocessors.1":[162]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":1}],"updated_date":"2026-08-01T09:00:35.917206","created_date":"2025-10-10T00:00:00"}
