{"id":"https://openalex.org/W3210245573","doi":"https://doi.org/10.1109/esscirc53450.2021.9567746","title":"A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions","display_name":"A Charge-Domain Computation-In-Memory Macro with Versatile All-Around-Wire-Capacitor for Variable-Precision Computation and Array-Embedded DA/AD Conversions","publication_year":2021,"publication_date":"2021-09-13","ids":{"openalex":"https://openalex.org/W3210245573","doi":"https://doi.org/10.1109/esscirc53450.2021.9567746","mag":"3210245573"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc53450.2021.9567746","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc53450.2021.9567746","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5089255813","display_name":"Gicheol Shin","orcid":null},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Gicheol Shin","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5056057968","display_name":"Donguk Seo","orcid":"https://orcid.org/0000-0003-3453-3940"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Donguk Seo","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5050397226","display_name":"Jaerok Kim","orcid":"https://orcid.org/0000-0002-4086-5215"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jaerok Kim","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081039356","display_name":"Johnny Rhe","orcid":"https://orcid.org/0000-0003-2603-974X"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Johnny Rhe","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100348726","display_name":"Eunyoung Lee","orcid":"https://orcid.org/0000-0001-7105-2199"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Eunyoung Lee","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101714614","display_name":"Seonho Kim","orcid":"https://orcid.org/0000-0002-8621-846X"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seonho Kim","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5042217495","display_name":"Soyoun Jeong","orcid":"https://orcid.org/0000-0002-2178-177X"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Soyoun Jeong","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5063908850","display_name":"Jong Hwan Ko","orcid":"https://orcid.org/0000-0003-4434-4318"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jong Hwan Ko","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040564153","display_name":"Yoonmyung Lee","orcid":"https://orcid.org/0000-0001-9468-1692"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Yoonmyung Lee","raw_affiliation_strings":["Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, Korea","institution_ids":["https://openalex.org/I848706"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I848706"],"apc_list":null,"apc_paid":null,"fwci":0.0983,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.43417052,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"123","last_page":"126"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12808","display_name":"Ferroelectric and Negative Capacitance Devices","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9979000091552734,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/overhead","display_name":"Overhead (engineering)","score":0.6406856775283813},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6353658437728882},{"id":"https://openalex.org/keywords/computation","display_name":"Computation","score":0.613405704498291},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5708486437797546},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.5477296113967896},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5386639833450317},{"id":"https://openalex.org/keywords/variable","display_name":"Variable (mathematics)","score":0.4966197609901428},{"id":"https://openalex.org/keywords/variable-capacitor","display_name":"Variable capacitor","score":0.4893931448459625},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.46673333644866943},{"id":"https://openalex.org/keywords/efficient-energy-use","display_name":"Efficient energy use","score":0.4161502718925476},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3621792793273926},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.35760194063186646},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2802390456199646},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21756473183631897},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.13694438338279724},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.07157549262046814}],"concepts":[{"id":"https://openalex.org/C2779960059","wikidata":"https://www.wikidata.org/wiki/Q7113681","display_name":"Overhead (engineering)","level":2,"score":0.6406856775283813},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6353658437728882},{"id":"https://openalex.org/C45374587","wikidata":"https://www.wikidata.org/wiki/Q12525525","display_name":"Computation","level":2,"score":0.613405704498291},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5708486437797546},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.5477296113967896},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5386639833450317},{"id":"https://openalex.org/C182365436","wikidata":"https://www.wikidata.org/wiki/Q50701","display_name":"Variable (mathematics)","level":2,"score":0.4966197609901428},{"id":"https://openalex.org/C171496939","wikidata":"https://www.wikidata.org/wiki/Q1347410","display_name":"Variable capacitor","level":4,"score":0.4893931448459625},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.46673333644866943},{"id":"https://openalex.org/C2742236","wikidata":"https://www.wikidata.org/wiki/Q924713","display_name":"Efficient energy use","level":2,"score":0.4161502718925476},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3621792793273926},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.35760194063186646},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2802390456199646},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21756473183631897},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.13694438338279724},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.07157549262046814},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc53450.2021.9567746","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc53450.2021.9567746","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":4,"referenced_works":["https://openalex.org/W2792893539","https://openalex.org/W2898913080","https://openalex.org/W2922487710","https://openalex.org/W3015432327"],"related_works":["https://openalex.org/W2371258795","https://openalex.org/W2154012053","https://openalex.org/W2067707080","https://openalex.org/W2068088818","https://openalex.org/W2585509534","https://openalex.org/W1840648860","https://openalex.org/W2004916302","https://openalex.org/W2135441272","https://openalex.org/W2358920450","https://openalex.org/W1994917736"],"abstract_inverted_index":{"A":[0,16],"charge-domain":[1,25],"SRAM-based":[2],"CIM":[3],"macro":[4],"is":[5,20],"proposed":[6],"to":[7,22,77],"implement":[8],"efficient":[9],"neural":[10],"accelerator":[11],"with":[12,28,34],"variable":[13],"input/weight/output":[14],"precisions.":[15],"versatile":[17],"All-Around-Wire-Capacitor":[18],"(AAWC)":[19],"introduced":[21],"enable":[23],"accurate":[24],"MAV":[26],"operation":[27],"1-5":[29,45],"bit":[30,46,54],"variable-precision":[31,43],"weight":[32],"capability":[33],"10T":[35],"SRAM":[36],"cell":[37],"structure.":[38],"The":[39],"AAWC":[40],"also":[41],"allows":[42],"array-embedded":[44,65],"digital-to-analog":[47],"(DA)":[48],"conversion":[49,57,67],"for":[50,58],"input,":[51],"and":[52,73],"1-6":[53],"analog-to-digital":[55],"(AD)":[56],"output":[59],"without":[60],"additional":[61],"passive":[62],"devices.":[63],"Such":[64],"DA/AD":[66],"scheme":[68],"significantly":[69],"reduces":[70],"area":[71],"overhead":[72],"simplifies":[74],"peripheral":[75],"circuits":[76],"achieve":[78],"high":[79,84],"array":[80],"efficiency":[81,86],"while":[82],"achieving":[83],"energy":[85],"of":[87],"24-330":[88],"TOPS/W.":[89]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}