{"id":"https://openalex.org/W2986197122","doi":"https://doi.org/10.1109/esscirc.2019.8902909","title":"Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN)","display_name":"Physically Tightly Coupled, Logically Loosely Coupled, Near-Memory BNN Accelerator (PTLL-BNN)","publication_year":2019,"publication_date":"2019-09-01","ids":{"openalex":"https://openalex.org/W2986197122","doi":"https://doi.org/10.1109/esscirc.2019.8902909","mag":"2986197122"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2019.8902909","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2019.8902909","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5023017360","display_name":"Yun-Chen Lo","orcid":"https://orcid.org/0000-0002-1324-7649"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Yun-Chen Lo","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061736639","display_name":"Yu-Chun Kuo","orcid":"https://orcid.org/0000-0001-5617-7815"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yu-Chun Kuo","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5032014006","display_name":"Yun-Sheng Chang","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Yun-Sheng Chang","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5069113085","display_name":"Jianhao Huang","orcid":"https://orcid.org/0000-0003-1490-2390"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jian-Hao Huang","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5059089862","display_name":"Jun-Shen Wu","orcid":"https://orcid.org/0000-0003-3816-3350"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jun-Shen Wu","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5106557460","display_name":"Wen-Chien Ting","orcid":"https://orcid.org/0000-0003-0282-6095"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Wen-Chien Ting","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5002800102","display_name":"Tai-Hsing Wen","orcid":null},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Tai-Hsing Wen","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007060812","display_name":"Ren-Shuo Liu","orcid":"https://orcid.org/0000-0002-5311-4955"},"institutions":[{"id":"https://openalex.org/I25846049","display_name":"National Tsing Hua University","ror":"https://ror.org/00zdnkx70","country_code":"TW","type":"education","lineage":["https://openalex.org/I25846049"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Ren-Shuo Liu","raw_affiliation_strings":["Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Tsing Hua University, Hsinchu, Taiwan","institution_ids":["https://openalex.org/I25846049"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5023017360"],"corresponding_institution_ids":["https://openalex.org/I25846049"],"apc_list":null,"apc_paid":null,"fwci":0.2024,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.55102628,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"241","last_page":"244"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10036","display_name":"Advanced Neural Network Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10502","display_name":"Advanced Memory and Neural Computing","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12702","display_name":"Brain Tumor Detection and Classification","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2808","display_name":"Neurology"},"field":{"id":"https://openalex.org/fields/28","display_name":"Neuroscience"},"domain":{"id":"https://openalex.org/domains/1","display_name":"Life Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.758691668510437},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.7307340502738953},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.47760722041130066},{"id":"https://openalex.org/keywords/hardware-acceleration","display_name":"Hardware acceleration","score":0.4724434018135071},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4565226435661316},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.4242561459541321},{"id":"https://openalex.org/keywords/memory-architecture","display_name":"Memory architecture","score":0.42300570011138916},{"id":"https://openalex.org/keywords/compiler","display_name":"Compiler","score":0.4154478907585144},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.20891985297203064},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14634078741073608}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.758691668510437},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.7307340502738953},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.47760722041130066},{"id":"https://openalex.org/C13164978","wikidata":"https://www.wikidata.org/wiki/Q600158","display_name":"Hardware acceleration","level":3,"score":0.4724434018135071},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4565226435661316},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.4242561459541321},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.42300570011138916},{"id":"https://openalex.org/C169590947","wikidata":"https://www.wikidata.org/wiki/Q47506","display_name":"Compiler","level":2,"score":0.4154478907585144},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.20891985297203064},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14634078741073608}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2019.8902909","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2019.8902909","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":21,"referenced_works":["https://openalex.org/W1677182931","https://openalex.org/W2260663238","https://openalex.org/W2289252105","https://openalex.org/W2300242332","https://openalex.org/W2515287984","https://openalex.org/W2585560244","https://openalex.org/W2752782242","https://openalex.org/W2794288888","https://openalex.org/W2898935766","https://openalex.org/W2899378420","https://openalex.org/W2921329602","https://openalex.org/W2922487710","https://openalex.org/W2949608135","https://openalex.org/W2963420686","https://openalex.org/W2965306467","https://openalex.org/W3024621361","https://openalex.org/W6692521979","https://openalex.org/W6698200048","https://openalex.org/W6760724898","https://openalex.org/W6760912325","https://openalex.org/W6765978677"],"related_works":["https://openalex.org/W4392590355","https://openalex.org/W3151633427","https://openalex.org/W4240253816","https://openalex.org/W2212894501","https://openalex.org/W3096456556","https://openalex.org/W2793465010","https://openalex.org/W3152699334","https://openalex.org/W2026052914","https://openalex.org/W2149373426","https://openalex.org/W2501971876"],"abstract_inverted_index":{"In":[0],"this":[1,115,130,151,172],"paper,":[2],"a":[3,82,133,194],"physically":[4,56],"tightly":[5,57],"coupled,":[6,9],"logically":[7,88],"loosely":[8,89],"near-memory":[10],"binary":[11],"neural":[12],"network":[13],"accelerator":[14,44,71,80,101,204,210],"(PTLL-BNN)":[15],"is":[16,45,67,72,81,205],"designed":[17],"and":[18,22,59,109,124,161,181,240],"fabricated.":[19],"Both":[20],"architecture-level":[21],"circuit-level":[23],"optimizations":[24],"are":[25,245],"presented.":[26],"From":[27,111],"the":[28,33,41,49,52,62,70,79,99,103,112,122,127,147,155,158,163,168,178,185,190,199,203,209,212,265,271],"perspective":[29],"of":[30,51,105,126,138,157,166,184,197,202,253,267],"processor":[31],"architecture,":[32],"PTLL-BNN":[34],"includes":[35],"two":[36],"new":[37],"design":[38,131],"choices.":[39],"First,":[40,129],"proposed":[42,100],"BNN":[43],"placed":[46],"close":[47],"to":[48,120,176,187,247,263],"SRAM":[50,64,159,244],"embedded":[53,93],"processors":[54,94],"(i.e.,":[55,87],"coupled":[58],"near-memory);":[60],"thus,":[61],"extra":[63],"cost":[65],"that":[66,150,252],"incurred":[68],"by":[69],"as":[73,75],"low":[74],"0.5":[76],"KB.":[77],"Second,":[78,146],"memory-mapped":[83],"IO":[84],"(MMIO)":[85],"device":[86],"coupled),":[90],"so":[91],"all":[92],"can":[95],"be":[96],"equipped":[97],"with":[98],"without":[102],"burden":[104],"changing":[106],"their":[107],"compilers":[108],"pipelines.":[110],"circuit":[113],"perspective,":[114],"work":[116,152,173],"employs":[117],"four":[118],"techniques":[119],"optimize":[121],"power":[123],"costs":[125],"accelerator.":[128,273],"adopts":[132],"unified":[134],"input-kernel-output":[135],"memory":[136],"instead":[137],"separate":[139],"ones,":[140],"which":[141],"many":[142],"previous":[143,254],"works":[144],"adopt.":[145],"data":[148],"layout":[149],"chooses":[153],"increases":[154],"sequentiality":[156],"accesses":[160],"reduces":[162],"buffer":[164],"size":[165],"storing":[167],"intermediate":[169],"values.":[170],"Third,":[171],"innovatively":[174],"proposes":[175],"fuse":[177],"max-pooling,":[179],"batch-normalization,":[180],"binarization":[182],"layers":[183],"BNNs":[186],"significantly":[188],"reduce":[189],"hardware":[191,201],"complexity.":[192],"Finally,":[193],"novel":[195],"methodology":[196],"generating":[198],"scheduler":[200],"included.":[206],"We":[207,257],"fabricate":[208],"using":[211,270],"TSMC":[213],"180":[214],"nm":[215],"technology.":[216],"The":[217,233],"chip":[218],"measurement":[219],"results":[220],"reach":[221],"91":[222],"GOP/s":[223,227,235,241],"on":[224],"average":[225],"(307":[226],"at":[228,230],"peak)":[229],"200":[231],"MHz.":[232],"achieved":[234],"per":[236,242],"million":[237],"logic":[238],"gates":[239],"KB":[243],"2.6":[246],"237":[248],"times":[249],"greater":[250],"than":[251],"works,":[255],"respectively.":[256],"also":[258],"realize":[259],"an":[260],"FPGA":[261],"system":[262],"demonstrate":[264],"recognition":[266],"CIFAR-10/100":[268],"images":[269],"fabricated":[272]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}