{"id":"https://openalex.org/W2986095991","doi":"https://doi.org/10.1109/esscirc.2019.8902873","title":"Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR","display_name":"Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR","publication_year":2019,"publication_date":"2019-09-01","ids":{"openalex":"https://openalex.org/W2986095991","doi":"https://doi.org/10.1109/esscirc.2019.8902873","mag":"2986095991"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2019.8902873","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2019.8902873","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5101768089","display_name":"Tianli Zhang","orcid":"https://orcid.org/0000-0002-9266-5397"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Tianli Zhang","raw_affiliation_strings":["State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028059173","display_name":"Yuefeng Cao","orcid":"https://orcid.org/0000-0003-1000-9079"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Yuefeng Cao","raw_affiliation_strings":["State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100681914","display_name":"Shumin Zhang","orcid":"https://orcid.org/0000-0003-2777-3938"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Shumin Zhang","raw_affiliation_strings":["State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5051205321","display_name":"Chixiao Chen","orcid":"https://orcid.org/0000-0002-5980-4236"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Chixiao Chen","raw_affiliation_strings":["Academy of Engineering and Technologies, Fudan University, Shanghai, PR China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Academy of Engineering and Technologies, Fudan University, Shanghai, PR China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025053306","display_name":"Fan Ye","orcid":"https://orcid.org/0000-0002-1089-1498"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Fan Ye","raw_affiliation_strings":["State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China","institution_ids":["https://openalex.org/I24943067"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5016448886","display_name":"Junyan Ren","orcid":"https://orcid.org/0000-0002-7799-6251"},"institutions":[{"id":"https://openalex.org/I24943067","display_name":"Fudan University","ror":"https://ror.org/013q1eq08","country_code":"CN","type":"education","lineage":["https://openalex.org/I24943067"]}],"countries":["CN"],"is_corresponding":false,"raw_author_name":"Junyan Ren","raw_affiliation_strings":["State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"State Key Lab of ASIC and Systems, Fudan University, Shanghai, PR China","institution_ids":["https://openalex.org/I24943067"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I24943067"],"apc_list":null,"apc_paid":null,"fwci":1.1964,"has_fulltext":false,"cited_by_count":42,"citation_normalized_percentile":{"value":0.77607206,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":96,"max":99},"biblio":{"volume":null,"issue":null,"first_page":"189","last_page":"192"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/spurious-free-dynamic-range","display_name":"Spurious-free dynamic range","score":0.9322516918182373},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7220221757888794},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.6741734743118286},{"id":"https://openalex.org/keywords/calibration","display_name":"Calibration","score":0.5934019684791565},{"id":"https://openalex.org/keywords/effective-number-of-bits","display_name":"Effective number of bits","score":0.5618126392364502},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5592164397239685},{"id":"https://openalex.org/keywords/comparator","display_name":"Comparator","score":0.516028881072998},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.5044223070144653},{"id":"https://openalex.org/keywords/residual","display_name":"Residual","score":0.5017135143280029},{"id":"https://openalex.org/keywords/12-bit","display_name":"12-bit","score":0.4922095835208893},{"id":"https://openalex.org/keywords/distortion","display_name":"Distortion (music)","score":0.4775168001651764},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.41355279088020325},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.3706737756729126},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.36814653873443604},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.21133270859718323},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17503571510314941},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.1325896680355072},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09704822301864624}],"concepts":[{"id":"https://openalex.org/C119293636","wikidata":"https://www.wikidata.org/wiki/Q657480","display_name":"Spurious-free dynamic range","level":3,"score":0.9322516918182373},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7220221757888794},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.6741734743118286},{"id":"https://openalex.org/C165838908","wikidata":"https://www.wikidata.org/wiki/Q736777","display_name":"Calibration","level":2,"score":0.5934019684791565},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.5618126392364502},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5592164397239685},{"id":"https://openalex.org/C155745195","wikidata":"https://www.wikidata.org/wiki/Q1164179","display_name":"Comparator","level":3,"score":0.516028881072998},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.5044223070144653},{"id":"https://openalex.org/C155512373","wikidata":"https://www.wikidata.org/wiki/Q287450","display_name":"Residual","level":2,"score":0.5017135143280029},{"id":"https://openalex.org/C2776310492","wikidata":"https://www.wikidata.org/wiki/Q3271420","display_name":"12-bit","level":3,"score":0.4922095835208893},{"id":"https://openalex.org/C126780896","wikidata":"https://www.wikidata.org/wiki/Q899871","display_name":"Distortion (music)","level":4,"score":0.4775168001651764},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.41355279088020325},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.3706737756729126},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.36814653873443604},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.21133270859718323},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17503571510314941},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.1325896680355072},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09704822301864624},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2019.8902873","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2019.8902873","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W2081904850","https://openalex.org/W2119144962","https://openalex.org/W2161642455","https://openalex.org/W2749655596","https://openalex.org/W2769243529","https://openalex.org/W2795846192","https://openalex.org/W2964299589","https://openalex.org/W6677580257"],"related_works":["https://openalex.org/W4206356469","https://openalex.org/W2511822798","https://openalex.org/W2904640696","https://openalex.org/W2341231357","https://openalex.org/W2942561789","https://openalex.org/W2542593952","https://openalex.org/W2759515872","https://openalex.org/W2783221760","https://openalex.org/W4390693196","https://openalex.org/W2207354743"],"abstract_inverted_index":{"The":[0,25,41,78],"paper":[1],"presents":[2],"a":[3,28],"machine-learning":[4],"based":[5],"calibration":[6],"scheme":[7,22,26],"for":[8],"split":[9,61],"pipelined-SAR":[10,62],"ADCs":[11,109],"with":[12,64,110],"open-loop":[13,111],"residual":[14],"amplifiers.":[15,112],"Different":[16],"from":[17],"conventional":[18],"methods,":[19],"the":[20,35,45,55,76,82,99,104],"proposed":[21],"is":[23,69],"prior-knowledge-free.":[24],"adopts":[27],"two-layer":[29],"neural":[30,42],"network,":[31],"and":[32,47,90],"directly":[33],"uses":[34],"bit-wise":[36],"comparator":[37],"results":[38,80],"as":[39],"inputs.":[40],"network":[43],"compensates":[44],"distortion":[46],"can":[48],"be":[49],"compressed":[50],"by":[51],"75%":[52],"due":[53],"to":[54,74],"network\u2019s":[56],"sparsity.":[57],"A":[58],"14-bit":[59],"60-MSps":[60],"ADC":[63,83],"gain":[65],"boosted":[66],"dynamic":[67],"amplifiers":[68],"fabricated":[70],"in":[71],"28nm":[72],"CMOS":[73],"validate":[75],"scheme.":[77],"measurement":[79],"show":[81],"achieves":[84,103],"an":[85,91],"SFDR":[86,106],"of":[87,93],"93.7":[88],"dB":[89],"ENOB":[92],"10.7b,":[94],"consuming":[95],"2.79":[96],"mW.":[97],"To":[98],"authors\u2019":[100],"knowledge,":[101],"it":[102],"best":[105],"among":[107],"Nyquist":[108]},"counts_by_year":[{"year":2026,"cited_by_count":4},{"year":2025,"cited_by_count":11},{"year":2024,"cited_by_count":11},{"year":2023,"cited_by_count":4},{"year":2022,"cited_by_count":3},{"year":2021,"cited_by_count":6},{"year":2020,"cited_by_count":3}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}
