{"id":"https://openalex.org/W2899182440","doi":"https://doi.org/10.1109/esscirc.2018.8494257","title":"A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS","display_name":"A 230mV-950mV 2.8Tbps/W Unified SHA256/SM3 Secure Hashing Hardware Accelerator in 14nm Tri-Gate CMOS","publication_year":2018,"publication_date":"2018-09-01","ids":{"openalex":"https://openalex.org/W2899182440","doi":"https://doi.org/10.1109/esscirc.2018.8494257","mag":"2899182440"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2018.8494257","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2018.8494257","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5078003656","display_name":"Vikram Suresh","orcid":"https://orcid.org/0000-0001-8879-1967"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Vikram Suresh","raw_affiliation_strings":["Circuits Research Lab, Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5075692568","display_name":"Sudhir Satpathy","orcid":"https://orcid.org/0000-0003-3511-3526"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhir Satpathy","raw_affiliation_strings":["Circuits Research Lab, Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039276616","display_name":"Sanu Mathew","orcid":"https://orcid.org/0000-0003-1344-7533"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanu Mathew","raw_affiliation_strings":["Circuits Research Lab, Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052106795","display_name":"Mark Anders","orcid":"https://orcid.org/0000-0001-5748-8420"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Anders","raw_affiliation_strings":["Circuits Research Lab, Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070239387","display_name":"Himanshu Kaul","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Himanshu Kaul","raw_affiliation_strings":["Circuits Research Lab, Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006348328","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-4220-3346"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["Circuits Research Lab, Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109340111","display_name":"Steven Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven Hsu","raw_affiliation_strings":["Circuits Research Lab, Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram Krishnamurthy","raw_affiliation_strings":["Circuits Research Lab, Intel Corporation, Hillsboro, OR"],"affiliations":[{"raw_affiliation_string":"Circuits Research Lab, Intel Corporation, Hillsboro, OR","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5078003656"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.7381,"has_fulltext":false,"cited_by_count":8,"citation_normalized_percentile":{"value":0.75274047,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"98","last_page":"101"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.9743000268936157,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11478","display_name":"Caching and Content Delivery","score":0.9743000268936157,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10587","display_name":"Autophagy in Disease and Therapy","score":0.973800003528595,"subfield":{"id":"https://openalex.org/subfields/2713","display_name":"Epidemiology"},"field":{"id":"https://openalex.org/fields/27","display_name":"Medicine"},"domain":{"id":"https://openalex.org/domains/4","display_name":"Health Sciences"}},{"id":"https://openalex.org/T12326","display_name":"Network Packet Processing and Optimization","score":0.9726999998092651,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/hash-function","display_name":"Hash function","score":0.6650592088699341},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6344249844551086},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6204805374145508},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5597192049026489},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.527080237865448},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.45371824502944946},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41834554076194763},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.32007765769958496},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2591628432273865},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.18081596493721008},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.14904701709747314},{"id":"https://openalex.org/keywords/optoelectronics","display_name":"Optoelectronics","score":0.1118767261505127}],"concepts":[{"id":"https://openalex.org/C99138194","wikidata":"https://www.wikidata.org/wiki/Q183427","display_name":"Hash function","level":2,"score":0.6650592088699341},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6344249844551086},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6204805374145508},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5597192049026489},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.527080237865448},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.45371824502944946},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41834554076194763},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.32007765769958496},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2591628432273865},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.18081596493721008},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.14904701709747314},{"id":"https://openalex.org/C49040817","wikidata":"https://www.wikidata.org/wiki/Q193091","display_name":"Optoelectronics","level":1,"score":0.1118767261505127},{"id":"https://openalex.org/C38652104","wikidata":"https://www.wikidata.org/wiki/Q3510521","display_name":"Computer security","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2018.8494257","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2018.8494257","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1523981315","https://openalex.org/W1985147001","https://openalex.org/W2042689779","https://openalex.org/W2044272551","https://openalex.org/W2071195621","https://openalex.org/W2126252444","https://openalex.org/W2520192810","https://openalex.org/W4235629799","https://openalex.org/W6631114413","https://openalex.org/W6646786583"],"related_works":["https://openalex.org/W4390550886","https://openalex.org/W3217463396","https://openalex.org/W2790557758","https://openalex.org/W2516396101","https://openalex.org/W3204929712","https://openalex.org/W4295102875","https://openalex.org/W2300671402","https://openalex.org/W2015457513","https://openalex.org/W1993041309","https://openalex.org/W2183015194"],"abstract_inverted_index":{"A":[0],"unified":[1],"SHA256/SM3":[2],"secure":[3],"hashing":[4],"hardware":[5],"accelerator":[6,46],"for":[7],"cross-geo":[8],"authentication":[9],"is":[10],"fabricated":[11],"in":[12,51],"14nm":[13],"tri-gate":[14],"CMOS,":[15],"with":[16,29],"a":[17,52,85],"throughput":[18,71],"of":[19,55,88],"9.5/8.3Gbps":[20],"respectively":[21],"measured":[22,90],"at":[23,69,91],"0.75V,":[24],"25\u00b0C.":[25],"Message":[26],"digest":[27],"pre-addition,":[28],"mode-multiplexed":[30],"digest/scheduler":[31],"completion":[32],"adders":[33],"and":[34,45],"distributed":[35],"final":[36],"hash":[37],"computation":[38],"reduces":[39],"critical":[40],"path":[41],"delay":[42],"by":[43,48],"14%":[44],"area":[47],"48%,":[49],"resulting":[50],"compact":[53],"layout":[54],"5992\u03bcm":[56],"<sup":[57],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[58],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[59],".":[60],"2/4-way":[61],"parallel":[62],"message":[63],"scheduler":[64,74],"enables":[65,84],"0.5/0.25\u00d7":[66],"frequency":[67],"scaling":[68],"iso-hash":[70],"enabling":[72],"35/62%":[73],"power":[75],"reduction.":[76],"Robust":[77],"sub-threshold":[78],"voltage":[79],"operation":[80],"down":[81],"to":[82],"230mV":[83],"peak":[86],"energy-efficiency":[87],"2.8Tbps/W":[89],"300mV.":[92]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
