{"id":"https://openalex.org/W2898683151","doi":"https://doi.org/10.1109/esscirc.2018.8494238","title":"34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms","display_name":"34.4Mbps 1.56Tbps/W DEFLATE Decompression Accelerator Featuring Block-Adaptive Huffman Decoder in 14nm Tri-Gate CMOS for IoT Platforms","publication_year":2018,"publication_date":"2018-09-01","ids":{"openalex":"https://openalex.org/W2898683151","doi":"https://doi.org/10.1109/esscirc.2018.8494238","mag":"2898683151"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2018.8494238","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2018.8494238","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5075692568","display_name":"Sudhir Satpathy","orcid":"https://orcid.org/0000-0003-3511-3526"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sudhir Satpathy","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5039276616","display_name":"Sanu Mathew","orcid":"https://orcid.org/0000-0003-1344-7533"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Sanu Mathew","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5078003656","display_name":"Vikram Suresh","orcid":"https://orcid.org/0000-0001-8879-1967"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vikram Suresh","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112628103","display_name":"Vinodh Gopal","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Vinodh Gopal","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5016784779","display_name":"James Guilford","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"James Guilford","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5052106795","display_name":"Mark Anders","orcid":"https://orcid.org/0000-0001-5748-8420"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mark Anders","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5081032347","display_name":"Himanshu Kaul","orcid":"https://orcid.org/0000-0003-1586-7486"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Himanshu Kaul","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006348328","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-4220-3346"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109340111","display_name":"Steven Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven Hsu","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5023288901","display_name":"Kam Krisnnamurthy","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kam Krisnnamurthy","raw_affiliation_strings":["Intel Corporation, Hillsboro, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Corporation, Hillsboro, USA","institution_ids":["https://openalex.org/I1343180700"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.3395,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.6187155,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"90","last_page":"93"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11269","display_name":"Algorithms and Data Compression","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11321","display_name":"Error Correcting Code Techniques","score":0.9977999925613403,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10901","display_name":"Advanced Data Compression Techniques","score":0.9927999973297119,"subfield":{"id":"https://openalex.org/subfields/1707","display_name":"Computer Vision and Pattern Recognition"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/firmware","display_name":"Firmware","score":0.8793914318084717},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7303407788276672},{"id":"https://openalex.org/keywords/huffman-coding","display_name":"Huffman coding","score":0.7227271199226379},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6898547410964966},{"id":"https://openalex.org/keywords/throughput","display_name":"Throughput","score":0.5725624561309814},{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.5571759939193726},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.5198662281036377},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.46530988812446594},{"id":"https://openalex.org/keywords/decoding-methods","display_name":"Decoding methods","score":0.4377446472644806},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.43337082862854004},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4115343987941742},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.38035473227500916},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.33049294352531433},{"id":"https://openalex.org/keywords/wireless","display_name":"Wireless","score":0.19494310021400452},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.18707218766212463},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.12483713030815125},{"id":"https://openalex.org/keywords/data-compression","display_name":"Data compression","score":0.11625257134437561},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.11233973503112793},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.09518364071846008}],"concepts":[{"id":"https://openalex.org/C67212190","wikidata":"https://www.wikidata.org/wiki/Q104851","display_name":"Firmware","level":2,"score":0.8793914318084717},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7303407788276672},{"id":"https://openalex.org/C46900642","wikidata":"https://www.wikidata.org/wiki/Q2647","display_name":"Huffman coding","level":3,"score":0.7227271199226379},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6898547410964966},{"id":"https://openalex.org/C157764524","wikidata":"https://www.wikidata.org/wiki/Q1383412","display_name":"Throughput","level":3,"score":0.5725624561309814},{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.5571759939193726},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5198662281036377},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.46530988812446594},{"id":"https://openalex.org/C57273362","wikidata":"https://www.wikidata.org/wiki/Q576722","display_name":"Decoding methods","level":2,"score":0.4377446472644806},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.43337082862854004},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4115343987941742},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.38035473227500916},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.33049294352531433},{"id":"https://openalex.org/C555944384","wikidata":"https://www.wikidata.org/wiki/Q249","display_name":"Wireless","level":2,"score":0.19494310021400452},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.18707218766212463},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.12483713030815125},{"id":"https://openalex.org/C78548338","wikidata":"https://www.wikidata.org/wiki/Q2493","display_name":"Data compression","level":2,"score":0.11625257134437561},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.11233973503112793},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.09518364071846008},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2018.8494238","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2018.8494238","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.9100000262260437}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1995317156","https://openalex.org/W2023751094","https://openalex.org/W2027066245","https://openalex.org/W2141657965","https://openalex.org/W2742345709","https://openalex.org/W2779883788","https://openalex.org/W6649045908"],"related_works":["https://openalex.org/W2582981600","https://openalex.org/W4389238932","https://openalex.org/W4387467152","https://openalex.org/W4212885212","https://openalex.org/W4379115910","https://openalex.org/W3010413952","https://openalex.org/W4253989935","https://openalex.org/W2810560948","https://openalex.org/W2070793896","https://openalex.org/W4206124993"],"abstract_inverted_index":{"A":[0],"9,296\u03bcm2DEFLATE":[1],"accelerator":[2],"targeted":[3],"for":[4,66],"firmware":[5],"decompression":[6],"in":[7,13,77],"battery-constrained":[8],"IoT":[9],"platforms":[10],"is":[11],"fabricated":[12],"14nm":[14],"tri-gate":[15],"CMOS,":[16],"and":[17,58,73,90],"operates":[18],"over":[19],"a":[20,35,78],"wide":[21],"supply":[22],"range":[23],"of":[24,34,37,42,70,88],"210-900m":[25],"V.":[26],"Dual-ALU":[27],"block-adaptive":[28],"Huffman":[29],"decoder":[30],"enables":[31],"simultaneous":[32],"evaluation":[33],"pair":[36],"code-lengths":[38],"with":[39,85],"opportunistic":[40],"skipping":[41],"non-existent":[43],"symbols":[44],"improving":[45],"throughput":[46,92],"by":[47],"34%":[48],"to":[49],"1.65Gb/s":[50],"at":[51,93,99],"750mV,":[52],"25\u00b0C,":[53],"while":[54],"in-line":[55],"literal":[56],"packing":[57],"fenced-record":[59],"generation":[60],"achieves":[61],"63%":[62],"memory":[63],"bandwidth":[64],"reduction":[65],"LZ77":[67],"reconstruction.":[68],"Absence":[69],"register":[71],"file":[72],"CAM":[74],"circuits":[75],"result":[76],"fully-synthesizable":[79],"implementation":[80],"enabling":[81],"ultra-low":[82],"voltage":[83],"operation":[84],"peak":[86],"energy-efficiency":[87],"1.56Tbps/W":[89],"34.4Mbps":[91],"22\u03bcW":[94],"total":[95],"power":[96],"consumption":[97],"measured":[98],"310mV.":[100]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2025,"cited_by_count":3},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":2},{"year":2019,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}
