{"id":"https://openalex.org/W2769943552","doi":"https://doi.org/10.1109/esscirc.2017.8094546","title":"A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology","display_name":"A 14-Bit, 1-ps resolution, two-step ring and 2D Vernier TDC in 130nm CMOS technology","publication_year":2017,"publication_date":"2017-09-01","ids":{"openalex":"https://openalex.org/W2769943552","doi":"https://doi.org/10.1109/esscirc.2017.8094546","mag":"2769943552"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2017.8094546","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2017.8094546","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5074357549","display_name":"Hechen Wang","orcid":"https://orcid.org/0000-0001-8437-7726"},"institutions":[{"id":"https://openalex.org/I82497590","display_name":"Auburn University","ror":"https://ror.org/02v80fc35","country_code":"US","type":"education","lineage":["https://openalex.org/I82497590"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Hechen Wang","raw_affiliation_strings":["Dept. of Electrical and Computer Eng., Auburn University, Auburn, AL"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Eng., Auburn University, Auburn, AL","institution_ids":["https://openalex.org/I82497590"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5035165376","display_name":"Fa Foster Dai","orcid":"https://orcid.org/0000-0003-1691-6649"},"institutions":[{"id":"https://openalex.org/I82497590","display_name":"Auburn University","ror":"https://ror.org/02v80fc35","country_code":"US","type":"education","lineage":["https://openalex.org/I82497590"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fa Foster Dai","raw_affiliation_strings":["Dept. of Electrical and Computer Eng., Auburn University, Auburn, AL"],"affiliations":[{"raw_affiliation_string":"Dept. of Electrical and Computer Eng., Auburn University, Auburn, AL","institution_ids":["https://openalex.org/I82497590"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":["https://openalex.org/A5074357549"],"corresponding_institution_ids":["https://openalex.org/I82497590"],"apc_list":null,"apc_paid":null,"fwci":1.7201,"has_fulltext":false,"cited_by_count":26,"citation_normalized_percentile":{"value":0.85861378,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"143","last_page":"146"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10299","display_name":"Photonic and Optical Devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vernier-scale","display_name":"Vernier scale","score":0.9273338913917542},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7329868078231812},{"id":"https://openalex.org/keywords/time-to-digital-converter","display_name":"Time-to-digital converter","score":0.4344763159751892},{"id":"https://openalex.org/keywords/resolution","display_name":"Resolution (logic)","score":0.4246559143066406},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.41836968064308167},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.32839691638946533},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.2913304269313812},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2733830213546753},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.11478909850120544},{"id":"https://openalex.org/keywords/optics","display_name":"Optics","score":0.10744866728782654}],"concepts":[{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.9273338913917542},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7329868078231812},{"id":"https://openalex.org/C99594498","wikidata":"https://www.wikidata.org/wiki/Q2434524","display_name":"Time-to-digital converter","level":4,"score":0.4344763159751892},{"id":"https://openalex.org/C138268822","wikidata":"https://www.wikidata.org/wiki/Q1051925","display_name":"Resolution (logic)","level":2,"score":0.4246559143066406},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.41836968064308167},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.32839691638946533},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.2913304269313812},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2733830213546753},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.11478909850120544},{"id":"https://openalex.org/C120665830","wikidata":"https://www.wikidata.org/wiki/Q14620","display_name":"Optics","level":1,"score":0.10744866728782654},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2017.8094546","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2017.8094546","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2017 - 43rd IEEE European Solid State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.75}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W2028941857","https://openalex.org/W2056154967","https://openalex.org/W2108435403","https://openalex.org/W2120912680","https://openalex.org/W2136657726","https://openalex.org/W2164828660","https://openalex.org/W2180973527","https://openalex.org/W2594781003","https://openalex.org/W2740439651","https://openalex.org/W3150579676","https://openalex.org/W6684221834","https://openalex.org/W6685863952"],"related_works":["https://openalex.org/W3158414702","https://openalex.org/W4389545333","https://openalex.org/W2296652335","https://openalex.org/W2182982459","https://openalex.org/W2112856903","https://openalex.org/W2541226935","https://openalex.org/W2120912680","https://openalex.org/W1984418134","https://openalex.org/W3022509112","https://openalex.org/W2547517791"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,15,19,58,109],"time-to-digital":[4],"(TDC)":[5],"design":[6],"with":[7,18,34,43,85,96],"large":[8],"detectable":[9,25],"range":[10,26],"and":[11,57,77],"fine":[12],"resolution,":[13],"combining":[14],"ring":[16,36],"TDC":[17,65,101],"2-dimentional":[20],"(2D)":[21],"Vernier":[22,45],"TDC.":[23],"The":[24,90],"has":[27],"been":[28],"greatly":[29,66],"increased":[30],"to":[31],"14":[32],"bits":[33],"the":[35,48,63,68,78,86],"structure.":[37],"A":[38,99],"1-ps":[39],"resolution":[40],"was":[41],"achieving":[42],"2D":[44,59,87],"architecture.":[46],"Utilizing":[47],"2":[49],"<sup":[50],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[51],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">nd</sup>":[52],"order":[53],"\u0394\u03a3":[54,97],"modulators":[55],"(SDM)":[56],"spiral":[60],"arbiter":[61,80],"array,":[62],"proposed":[64],"mitigates":[67],"quantization":[69],"errors":[70,83],"introduced":[71],"by":[72],"digitally":[73],"controlled":[74],"delay":[75],"cells":[76],"intrinsic":[79],"line":[81],"folding":[82],"associated":[84],"array":[88],"topology.":[89],"measured":[91],"maximum":[92],"DNL/INL":[93],"are":[94],"0.41/0.79ps":[95],"linearization.":[98],"prototype":[100],"chip":[102],"fabricated":[103],"in":[104],"130nm":[105],"CMOS":[106],"technology":[107],"achieves":[108],"conversion":[110],"rate":[111],"of":[112],"10":[113],"MS/s":[114],"while":[115],"consumes":[116],"2.4":[117],"mW":[118],"power.":[119]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2023,"cited_by_count":5},{"year":2022,"cited_by_count":2},{"year":2021,"cited_by_count":5},{"year":2020,"cited_by_count":4},{"year":2019,"cited_by_count":3},{"year":2018,"cited_by_count":4},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}