{"id":"https://openalex.org/W2538401073","doi":"https://doi.org/10.1109/esscirc.2016.7598311","title":"A 0.0175mm<sup>2</sup>600\u00b5W 32kHz input 307MHz output PLL with 190ps&lt;inf&gt;rms&lt;/inf&gt; jitter in 28nm FD-SOI","display_name":"A 0.0175mm<sup>2</sup>600\u00b5W 32kHz input 307MHz output PLL with 190ps&lt;inf&gt;rms&lt;/inf&gt; jitter in 28nm FD-SOI","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2538401073","doi":"https://doi.org/10.1109/esscirc.2016.7598311","mag":"2538401073"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2016.7598311","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2016.7598311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5058898812","display_name":"Abhirup Lahiri","orcid":null},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Abhirup Lahiri","raw_affiliation_strings":["Technology Research and Development Group, STMicroelectronics, Noida, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology Research and Development Group, STMicroelectronics, Noida, India","institution_ids":["https://openalex.org/I4210094169"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5007909345","display_name":"Nitin Gupta","orcid":"https://orcid.org/0000-0003-2750-2003"},"institutions":[{"id":"https://openalex.org/I4210094169","display_name":"STMicroelectronics (India)","ror":"https://ror.org/00ft7bw25","country_code":"IN","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210094169"]}],"countries":["IN"],"is_corresponding":false,"raw_author_name":"Nitin Gupta","raw_affiliation_strings":["Technology Research and Development Group, STMicroelectronics, Noida, India"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Technology Research and Development Group, STMicroelectronics, Noida, India","institution_ids":["https://openalex.org/I4210094169"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.186,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.59426693,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":"59","issue":null,"first_page":"339","last_page":"342"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9980999827384949,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9961000084877014,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.8598719835281372},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.7864760160446167},{"id":"https://openalex.org/keywords/voltage-controlled-oscillator","display_name":"Voltage-controlled oscillator","score":0.729010820388794},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5399008393287659},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.5326972007751465},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5297808647155762},{"id":"https://openalex.org/keywords/capacitance","display_name":"Capacitance","score":0.5030021071434021},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4914447069168091},{"id":"https://openalex.org/keywords/pll-multibit","display_name":"PLL multibit","score":0.48910409212112427},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.44927725195884705},{"id":"https://openalex.org/keywords/phase-noise","display_name":"Phase noise","score":0.430447518825531},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.427204430103302},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.3419753313064575},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.22766244411468506},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.15354236960411072}],"concepts":[{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.8598719835281372},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.7864760160446167},{"id":"https://openalex.org/C5291336","wikidata":"https://www.wikidata.org/wiki/Q852341","display_name":"Voltage-controlled oscillator","level":3,"score":0.729010820388794},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5399008393287659},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.5326972007751465},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5297808647155762},{"id":"https://openalex.org/C30066665","wikidata":"https://www.wikidata.org/wiki/Q164399","display_name":"Capacitance","level":3,"score":0.5030021071434021},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4914447069168091},{"id":"https://openalex.org/C77881186","wikidata":"https://www.wikidata.org/wiki/Q7119642","display_name":"PLL multibit","level":4,"score":0.48910409212112427},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.44927725195884705},{"id":"https://openalex.org/C89631360","wikidata":"https://www.wikidata.org/wiki/Q1428766","display_name":"Phase noise","level":2,"score":0.430447518825531},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.427204430103302},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.3419753313064575},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.22766244411468506},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.15354236960411072},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0},{"id":"https://openalex.org/C17525397","wikidata":"https://www.wikidata.org/wiki/Q176140","display_name":"Electrode","level":2,"score":0.0},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2016.7598311","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2016.7598311","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8500000238418579}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1991259611","https://openalex.org/W1999997320","https://openalex.org/W2034890308","https://openalex.org/W2105554928","https://openalex.org/W2153743315"],"related_works":["https://openalex.org/W1576949837","https://openalex.org/W1486070987","https://openalex.org/W1994021281","https://openalex.org/W1600405202","https://openalex.org/W2976219355","https://openalex.org/W2301158783","https://openalex.org/W1972664199","https://openalex.org/W2133120878","https://openalex.org/W2369672785","https://openalex.org/W2376956425"],"abstract_inverted_index":{"A":[0],"32":[1],"kHz":[2],"input":[3,23],"analog":[4],"phase-locked":[5],"loop":[6],"(PLL)":[7],"is":[8,29],"proposed":[9],"which":[10],"employs:":[11],"(i)":[12],"active":[13],"capacitor":[14,33],"multiplication":[15],"technique":[16,39,56],"for":[17,31,40,57],"reducing":[18],"PLL":[19,49,68,98],"area":[20,92],"wherein":[21],"the":[22,27,67],"parasitic":[24],"capacitance":[25],"from":[26],"VCO":[28],"utilized":[30],"loop-filter":[32,36],"realization,":[34],"(ii)":[35],"noise":[37,43],"reduction":[38,55],"lowering":[41],"its":[42],"contribution":[44],"on":[45],"integrated":[46,74],"jitter":[47,75],"at":[48],"output":[50],"and":[51,93],"(iii)":[52],"charge-pump":[53],"leakage":[54],"improving":[58],"reference-spur":[59],"performance.":[60],"Realized":[61],"in":[62],"28nm":[63],"UTBB":[64],"FD-SOI":[65],"process,":[66],"outputs":[69],"307.2MHz":[70],"clock,":[71],"provides":[72],"an":[73,100],"of":[76,85,102],"190ps":[77],"<sub":[78],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[79,90],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">rms</sub>":[80],",":[81],"has":[82,99],"reference":[83],"spur":[84],"-59.5dB,":[86],"occupies":[87],"0.0175mm":[88],"<sup":[89],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[91],"consumes":[94],"600\u03bcW":[95],"power.":[96],"The":[97],"FOM":[101],"-196.6dB.":[103]},"counts_by_year":[{"year":2017,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
