{"id":"https://openalex.org/W2537504266","doi":"https://doi.org/10.1109/esscirc.2016.7598269","title":"A 12b 180MS/s 0.068mm<sup>2</sup> pipelined-SAR ADC with merged-residue DAC for noise reduction","display_name":"A 12b 180MS/s 0.068mm<sup>2</sup> pipelined-SAR ADC with merged-residue DAC for noise reduction","publication_year":2016,"publication_date":"2016-09-01","ids":{"openalex":"https://openalex.org/W2537504266","doi":"https://doi.org/10.1109/esscirc.2016.7598269","mag":"2537504266"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2016.7598269","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2016.7598269","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5028637596","display_name":"Jianyu Zhong","orcid":"https://orcid.org/0000-0001-5761-2209"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":true,"raw_author_name":"Jianyu Zhong","raw_affiliation_strings":["Dept. of ECE, Faculty of Science and Technology, State-Key Laboratory of Analog and Mixed Signal VLSI, University of Macau, Macao, China"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, Faculty of Science and Technology, State-Key Laboratory of Analog and Mixed Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071933088","display_name":"Yan Zhu","orcid":"https://orcid.org/0000-0002-8298-3244"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Yan Zhu","raw_affiliation_strings":["Dept. of ECE, Faculty of Science and Technology, State-Key Laboratory of Analog and Mixed Signal VLSI, University of Macau, Macao, China"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, Faculty of Science and Technology, State-Key Laboratory of Analog and Mixed Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035229843","display_name":"Chi\u2010Hang Chan","orcid":"https://orcid.org/0000-0002-7635-1101"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Chi-Hang Chan","raw_affiliation_strings":["Dept. of ECE, Faculty of Science and Technology, State-Key Laboratory of Analog and Mixed Signal VLSI, University of Macau, Macao, China"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, Faculty of Science and Technology, State-Key Laboratory of Analog and Mixed Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5073702117","display_name":"Sai\u2010Weng Sin","orcid":"https://orcid.org/0000-0001-9346-8291"},"institutions":[{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["MO"],"is_corresponding":false,"raw_author_name":"Sai-Weng Sin","raw_affiliation_strings":["Dept. of ECE, Faculty of Science and Technology, State-Key Laboratory of Analog and Mixed Signal VLSI, University of Macau, Macao, China"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, Faculty of Science and Technology, State-Key Laboratory of Analog and Mixed Signal VLSI, University of Macau, Macao, China","institution_ids":["https://openalex.org/I204512498"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5061042931","display_name":"U Seng\u2010Pan","orcid":null},"institutions":[{"id":"https://openalex.org/I1335490905","display_name":"Synopsys (Switzerland)","ror":"https://ror.org/03mb54f81","country_code":"CH","type":"company","lineage":["https://openalex.org/I1335490905","https://openalex.org/I4210088951"]},{"id":"https://openalex.org/I204512498","display_name":"University of Macau","ror":"https://ror.org/01r4q9n85","country_code":"MO","type":"education","lineage":["https://openalex.org/I204512498"]}],"countries":["CH","MO"],"is_corresponding":false,"raw_author_name":"U. Seng-Pan","raw_affiliation_strings":["Dept. of ECE, University of Macau, Taipa, Macau, MO","Synopsys Macau Ltd"],"affiliations":[{"raw_affiliation_string":"Dept. of ECE, University of Macau, Taipa, Macau, MO","institution_ids":["https://openalex.org/I204512498"]},{"raw_affiliation_string":"Synopsys Macau Ltd","institution_ids":["https://openalex.org/I1335490905"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5106943352","display_name":"Rui P. Martins","orcid":"https://orcid.org/0000-0003-2821-648X"},"institutions":[{"id":"https://openalex.org/I203847022","display_name":"Instituto Polit\u00e9cnico de Lisboa","ror":"https://ror.org/04ea70f07","country_code":"PT","type":"education","lineage":["https://openalex.org/I203847022"]},{"id":"https://openalex.org/I141596103","display_name":"University of Lisbon","ror":"https://ror.org/01c27hj86","country_code":"PT","type":"education","lineage":["https://openalex.org/I141596103"]}],"countries":["PT"],"is_corresponding":false,"raw_author_name":"R.P. Martins","raw_affiliation_strings":["Instituto Superior T\u00e9cnico/Universidade de Lisboa, Lisbon, Portugal"],"affiliations":[{"raw_affiliation_string":"Instituto Superior T\u00e9cnico/Universidade de Lisboa, Lisbon, Portugal","institution_ids":["https://openalex.org/I203847022","https://openalex.org/I141596103"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5028637596"],"corresponding_institution_ids":["https://openalex.org/I204512498"],"apc_list":null,"apc_paid":null,"fwci":1.0256,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.77069064,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"169","last_page":"172"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11992","display_name":"CCD and CMOS Imaging Sensors","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.755436897277832},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.7349013090133667},{"id":"https://openalex.org/keywords/interleaving","display_name":"Interleaving","score":0.69651198387146},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6778906583786011},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.5848584771156311},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5443671345710754},{"id":"https://openalex.org/keywords/converters","display_name":"Converters","score":0.4898090064525604},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4640483260154724},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34893518686294556},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.25213924050331116},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.22212618589401245},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.20513147115707397}],"concepts":[{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.755436897277832},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.7349013090133667},{"id":"https://openalex.org/C28034677","wikidata":"https://www.wikidata.org/wiki/Q17092530","display_name":"Interleaving","level":2,"score":0.69651198387146},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6778906583786011},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.5848584771156311},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5443671345710754},{"id":"https://openalex.org/C2778422915","wikidata":"https://www.wikidata.org/wiki/Q10302051","display_name":"Converters","level":3,"score":0.4898090064525604},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4640483260154724},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34893518686294556},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.25213924050331116},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.22212618589401245},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.20513147115707397},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2016.7598269","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2016.7598269","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8899999856948853,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1979509961","https://openalex.org/W1981215785","https://openalex.org/W2005378264","https://openalex.org/W2005806893","https://openalex.org/W2028470944","https://openalex.org/W2073537459","https://openalex.org/W2085967153","https://openalex.org/W2089267425","https://openalex.org/W2147723118","https://openalex.org/W4244619305"],"related_works":["https://openalex.org/W2389051085","https://openalex.org/W1901012776","https://openalex.org/W2330343234","https://openalex.org/W2463883322","https://openalex.org/W2814468324","https://openalex.org/W2229382548","https://openalex.org/W2391789612","https://openalex.org/W2389236462","https://openalex.org/W2161636646","https://openalex.org/W3173839886"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"a":[3,21,31,78,89,94],"12b":[4],"180":[5],"MS/s":[6],"partial-interleaving":[7],"Pipelined-SAR":[8],"analog-to-digital":[9],"converter":[10],"(ADC).":[11],"The":[12,39,70],"1":[13],"<sup":[14],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[15],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">st</sup>":[16],"-stage":[17],"is":[18,60],"implemented":[19],"with":[20,53,84],"2b/cycle":[22,44],"SAR":[23],"ADC":[24,72],"for":[25,66],"high":[26],"speed,":[27],"where":[28],"we":[29],"propose":[30],"merged-residue-DAC":[32],"technique":[33],"to":[34,62,93],"improve":[35],"the":[36,57,64],"noise":[37],"performance.":[38],"capacitor":[40],"pre-charging":[41,65],"in":[42,74],"conventional":[43],"operation":[45],"wastes":[46],"settling":[47],"time":[48],"and":[49],"switching":[50,58],"energy,":[51],"while":[52],"this":[54],"design":[55],"approach":[56],"procedure":[59],"optimized":[61],"avoid":[63],"tri-level":[67],"reference":[68],"generation.":[69],"prototype":[71],"fabricated":[73],"65nm":[75],"CMOS":[76],"achieves":[77],"SNDR":[79],"of":[80,97],"63.8dB":[81],"@DC":[82,96],"input":[83],"6mW":[85],"power":[86],"dissipation":[87],"from":[88],"1.2V":[90],"supply,":[91],"leading":[92],"FoM":[95],"26.3":[98],"fJ/conv.-step.":[99]},"counts_by_year":[{"year":2022,"cited_by_count":1},{"year":2019,"cited_by_count":2},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}