{"id":"https://openalex.org/W2046750594","doi":"https://doi.org/10.1109/esscirc.2013.6649067","title":"All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate","display_name":"All-digital process-variation-calibrated timing generator for ATE with 1.95-ps resolution and a maximum 1.2-GHz test rate","publication_year":2013,"publication_date":"2013-09-01","ids":{"openalex":"https://openalex.org/W2046750594","doi":"https://doi.org/10.1109/esscirc.2013.6649067","mag":"2046750594"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2013.6649067","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2013.6649067","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5084041151","display_name":"Kyungho Ryu","orcid":"https://orcid.org/0000-0002-0354-4797"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyungho Ryu","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109180346","display_name":"Dong\u2010Hoon Jung","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dong-Hoon Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037010076","display_name":"Seong\u2010Ook Jung","orcid":"https://orcid.org/0000-0003-0757-2581"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seong-Ook Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"[Sch. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea]","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":0.9602,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.78833081,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"57","issue":null,"first_page":"41","last_page":"44"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vernier-scale","display_name":"Vernier scale","score":0.7401103377342224},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.568162202835083},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.5418314933776855},{"id":"https://openalex.org/keywords/generator","display_name":"Generator (circuit theory)","score":0.5075124502182007},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.5057759284973145},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49927639961242676},{"id":"https://openalex.org/keywords/application-specific-integrated-circuit","display_name":"Application-specific integrated circuit","score":0.477543443441391},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.450699120759964},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4342319071292877},{"id":"https://openalex.org/keywords/signal-generator","display_name":"Signal generator","score":0.4165096879005432},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3453769087791443},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.32259809970855713},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.2960139513015747},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.27081382274627686},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.2607882022857666},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.23792904615402222},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20863077044487},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.19480004906654358},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1435171365737915},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.1051081120967865}],"concepts":[{"id":"https://openalex.org/C69710193","wikidata":"https://www.wikidata.org/wiki/Q14946576","display_name":"Vernier scale","level":2,"score":0.7401103377342224},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.568162202835083},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.5418314933776855},{"id":"https://openalex.org/C2780992000","wikidata":"https://www.wikidata.org/wiki/Q17016113","display_name":"Generator (circuit theory)","level":3,"score":0.5075124502182007},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.5057759284973145},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49927639961242676},{"id":"https://openalex.org/C77390884","wikidata":"https://www.wikidata.org/wiki/Q217302","display_name":"Application-specific integrated circuit","level":2,"score":0.477543443441391},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.450699120759964},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4342319071292877},{"id":"https://openalex.org/C207912722","wikidata":"https://www.wikidata.org/wiki/Q1259123","display_name":"Signal generator","level":3,"score":0.4165096879005432},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3453769087791443},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.32259809970855713},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.2960139513015747},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.27081382274627686},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.2607882022857666},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.23792904615402222},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20863077044487},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.19480004906654358},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1435171365737915},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.1051081120967865},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.0},{"id":"https://openalex.org/C1276947","wikidata":"https://www.wikidata.org/wiki/Q333","display_name":"Astronomy","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2013.6649067","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2013.6649067","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 Proceedings of the ESSCIRC (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8500000238418579}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W116908809","https://openalex.org/W1494927921","https://openalex.org/W2096434843","https://openalex.org/W2118721819","https://openalex.org/W2132876868","https://openalex.org/W2145199955","https://openalex.org/W2147078733","https://openalex.org/W2148093371","https://openalex.org/W2169436946","https://openalex.org/W2788212596","https://openalex.org/W6677620656","https://openalex.org/W6681455977"],"related_works":["https://openalex.org/W2054844037","https://openalex.org/W2069827955","https://openalex.org/W3158414702","https://openalex.org/W3083903997","https://openalex.org/W2169618112","https://openalex.org/W2130851959","https://openalex.org/W2777227180","https://openalex.org/W2790711866","https://openalex.org/W2128209345","https://openalex.org/W2366985852"],"abstract_inverted_index":{"We":[0],"propose":[1],"a":[2,14,29,72,78],"timing":[3,73],"generator":[4,37],"for":[5],"use":[6],"in":[7],"high-performance":[8],"automatic":[9],"testing":[10],"equipment":[11],"that":[12],"achieves":[13],"high,":[15],"wide-range":[16],"test":[17,64],"cycle":[18,65],"frequency":[19,66],"and":[20,28,48,84],"process":[21],"variation":[22],"tolerance":[23],"using":[24,56],"four":[25],"sub-timing":[26,36],"generators":[27],"CLK":[30],"<sub":[31],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[32,91],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">RATE</sub>":[33],"divider.":[34],"Each":[35],"is":[38],"composed":[39],"of":[40,67,75,81,87],"an":[41,44,49,62,85],"edge":[42],"vernier,":[43],"integer":[45],"delay":[46],"generator,":[47],"offset":[50],"canceller.":[51],"A":[52],"prototype":[53],"chip":[54],"fabricated":[55],"0.13-\u03bcm":[57],"CMOS":[58],"technology":[59],"can":[60],"achieve":[61],"arbitrary":[63],"up":[68],"to":[69],"1.2":[70],"GHz,":[71],"resolution":[74],"1.95":[76],"ps,":[77],"power":[79],"consumption":[80],"90":[82],"mW,":[83],"area":[86],"1.5":[88],"mm":[89],"<sup":[90],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[92],".":[93]},"counts_by_year":[{"year":2024,"cited_by_count":1},{"year":2022,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2018,"cited_by_count":2},{"year":2017,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}