{"id":"https://openalex.org/W2066428821","doi":"https://doi.org/10.1109/esscirc.2012.6341288","title":"A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction","display_name":"A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction","publication_year":2012,"publication_date":"2012-09-01","ids":{"openalex":"https://openalex.org/W2066428821","doi":"https://doi.org/10.1109/esscirc.2012.6341288","mag":"2066428821"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2012.6341288","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2012.6341288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Proceedings of the ESSCIRC (ESSCIRC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109180346","display_name":"Dong\u2010Hoon Jung","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Dong-Hoon Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","School of Electrical and Electronic Engineering, Yonsei University , Seoul , Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University , Seoul , Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5084041151","display_name":"Kyungho Ryu","orcid":"https://orcid.org/0000-0002-0354-4797"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Kyungho Ryu","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","School of Electrical and Electronic Engineering, Yonsei University , Seoul , Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University , Seoul , Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"middle","author":{"id":null,"display_name":"Jung-Hyun Park","orcid":null},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Jung-Hyun Park","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","School of Electrical and Electronic Engineering, Yonsei University , Seoul , Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University , Seoul , Korea","institution_ids":["https://openalex.org/I193775966"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037010076","display_name":"Seong\u2010Ook Jung","orcid":"https://orcid.org/0000-0003-0757-2581"},"institutions":[{"id":"https://openalex.org/I193775966","display_name":"Yonsei University","ror":"https://ror.org/01wjejq96","country_code":"KR","type":"education","lineage":["https://openalex.org/I193775966"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Seong-Ook Jung","raw_affiliation_strings":["School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","School of Electrical and Electronic Engineering, Yonsei University , Seoul , Korea"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea","institution_ids":["https://openalex.org/I193775966"]},{"raw_affiliation_string":"School of Electrical and Electronic Engineering, Yonsei University , Seoul , Korea","institution_ids":["https://openalex.org/I193775966"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I193775966"],"apc_list":null,"apc_paid":null,"fwci":1.7488,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.86087975,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"181","last_page":"184"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9980000257492065,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.8704570531845093},{"id":"https://openalex.org/keywords/delay-locked-loop","display_name":"Delay-locked loop","score":0.7599486708641052},{"id":"https://openalex.org/keywords/loop","display_name":"Loop (graph theory)","score":0.6696330308914185},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.5550181269645691},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.520613431930542},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5166140198707581},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5010769367218018},{"id":"https://openalex.org/keywords/closed-loop","display_name":"Closed loop","score":0.4338011145591736},{"id":"https://openalex.org/keywords/control-theory","display_name":"Control theory (sociology)","score":0.36584532260894775},{"id":"https://openalex.org/keywords/phase-locked-loop","display_name":"Phase-locked loop","score":0.36406409740448},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.36118608713150024},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.26314517855644226},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.21925291419029236},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.15315628051757812},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1417372226715088},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.13873609900474548},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.1159663200378418}],"concepts":[{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.8704570531845093},{"id":"https://openalex.org/C190462668","wikidata":"https://www.wikidata.org/wiki/Q492265","display_name":"Delay-locked loop","level":4,"score":0.7599486708641052},{"id":"https://openalex.org/C184670325","wikidata":"https://www.wikidata.org/wiki/Q512604","display_name":"Loop (graph theory)","level":2,"score":0.6696330308914185},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.5550181269645691},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.520613431930542},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5166140198707581},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5010769367218018},{"id":"https://openalex.org/C3019251811","wikidata":"https://www.wikidata.org/wiki/Q5135346","display_name":"Closed loop","level":2,"score":0.4338011145591736},{"id":"https://openalex.org/C47446073","wikidata":"https://www.wikidata.org/wiki/Q5165890","display_name":"Control theory (sociology)","level":3,"score":0.36584532260894775},{"id":"https://openalex.org/C12707504","wikidata":"https://www.wikidata.org/wiki/Q52637","display_name":"Phase-locked loop","level":3,"score":0.36406409740448},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.36118608713150024},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.26314517855644226},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.21925291419029236},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.15315628051757812},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1417372226715088},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.13873609900474548},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.1159663200378418},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.0},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C2775924081","wikidata":"https://www.wikidata.org/wiki/Q55608371","display_name":"Control (management)","level":2,"score":0.0},{"id":"https://openalex.org/C133731056","wikidata":"https://www.wikidata.org/wiki/Q4917288","display_name":"Control engineering","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2012.6341288","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2012.6341288","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 Proceedings of the ESSCIRC (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.8999999761581421}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W1558158353","https://openalex.org/W1997549152","https://openalex.org/W2043584381","https://openalex.org/W2110921254","https://openalex.org/W2111592345","https://openalex.org/W2111894524","https://openalex.org/W2115448026","https://openalex.org/W2122144284","https://openalex.org/W2126227985","https://openalex.org/W4236811439","https://openalex.org/W6676589753","https://openalex.org/W6818034446"],"related_works":["https://openalex.org/W2354050524","https://openalex.org/W2083878249","https://openalex.org/W2401743820","https://openalex.org/W2066428821","https://openalex.org/W3177439118","https://openalex.org/W4295813049","https://openalex.org/W2119216036","https://openalex.org/W2389594899","https://openalex.org/W2144109350","https://openalex.org/W2976219355"],"abstract_inverted_index":{"In":[0],"this":[1,28],"paper,":[2],"we":[3,44],"propose":[4,46],"a":[5,10,33,47,60,65],"delay-locked":[6],"loop":[7],"(DLL)":[8],"with":[9,64],"closed-loop":[11],"duty-cycle":[12,107],"correction":[13],"(DCC)":[14],"circuit.":[15],"The":[16,54,71,82],"proposed":[17,55,88,102,128],"DCC":[18,42],"circuit":[19],"does":[20],"not":[21],"require":[22],"additional":[23],"blocks":[24],"for":[25,113],"DCC,":[26],"and":[27,38,111,122],"enables":[29],"it":[30],"to":[31,94,120],"have":[32],"significantly":[34],"reduced":[35],"power":[36,124],"consumption":[37,125],"area.":[39],"To":[40],"increase":[41],"accuracy,":[43],"also":[45],"duty":[48,116],"cycle":[49,117],"keeping":[50],"fine":[51],"delay":[52],"line.":[53],"DLL":[56,89,103,129],"is":[57,75,90,130],"implemented":[58],"using":[59],"0.13":[61],"\u03bcm":[62],"process":[63],"supply":[66],"voltage":[67],"of":[68,86,126],"1.2":[69],"V.":[70],"active":[72],"chip":[73],"area":[74],"0.02":[76],"mm":[77],"<sup":[78],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[79],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[80],".":[81],"operating":[83,99],"frequency":[84],"range":[85],"the":[87,101,123,127],"from":[91,118],"400":[92],"MHz":[93],"800":[95],"MHz.":[96],"At":[97],"all":[98],"frequencies,":[100],"achieves":[104],"an":[105,114],"output":[106],"error":[108],"between":[109],"-0.8%":[110],"1.04%":[112],"input":[115],"30%":[119],"70%":[121],"3.84":[131],"mW.":[132]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":2},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":1},{"year":2015,"cited_by_count":2},{"year":2014,"cited_by_count":3},{"year":2013,"cited_by_count":2}],"updated_date":"2026-06-26T08:34:08.712188","created_date":"2025-10-10T00:00:00"}