{"id":"https://openalex.org/W2158915695","doi":"https://doi.org/10.1109/esscirc.2011.6044897","title":"12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains","display_name":"12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains","publication_year":2011,"publication_date":"2011-09-01","ids":{"openalex":"https://openalex.org/W2158915695","doi":"https://doi.org/10.1109/esscirc.2011.6044897","mag":"2158915695"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2011.6044897","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2011.6044897","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5108573399","display_name":"Atsushi Muramatsu","orcid":null},"institutions":[{"id":"https://openalex.org/I4210125918","display_name":"Semiconductor Energy Laboratory (Japan)","ror":"https://ror.org/02vszc135","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210125918"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Atsushi Muramatsu","raw_affiliation_strings":["Semiconductor Technology Academic Research Center, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Semiconductor Technology Academic Research Center, Japan","institution_ids":["https://openalex.org/I4210125918"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036785948","display_name":"Tadashi Yasufuku","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tadashi Yasufuku","raw_affiliation_strings":["University of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005079654","display_name":"Masahiro Nomura","orcid":"https://orcid.org/0000-0003-3706-4836"},"institutions":[{"id":"https://openalex.org/I4210125918","display_name":"Semiconductor Energy Laboratory (Japan)","ror":"https://ror.org/02vszc135","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210125918"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masahiro Nomura","raw_affiliation_strings":["Semiconductor Technology Academic Research Center, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Semiconductor Technology Academic Research Center, Japan","institution_ids":["https://openalex.org/I4210125918"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5003282110","display_name":"Makoto Takamiya","orcid":"https://orcid.org/0000-0003-0289-7790"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Takamiya","raw_affiliation_strings":["University of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008563407","display_name":"Hirofumi Shinohara","orcid":"https://orcid.org/0000-0001-5589-8397"},"institutions":[{"id":"https://openalex.org/I4210125918","display_name":"Semiconductor Energy Laboratory (Japan)","ror":"https://ror.org/02vszc135","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210125918"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hirofumi Shinohara","raw_affiliation_strings":["Semiconductor Technology Academic Research Center, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Semiconductor Technology Academic Research Center, Japan","institution_ids":["https://openalex.org/I4210125918"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112189116","display_name":"Takayasu Sakurai","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Takayasu Sakurai","raw_affiliation_strings":["University of Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"University of Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.4475,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.63206301,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"191","last_page":"194"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4696718156337738},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.4238005578517914},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.42167532444000244},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.4216492772102356},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.3690292239189148},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.34841692447662354},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3128083348274231},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.2081598937511444},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.18470358848571777},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1586504578590393},{"id":"https://openalex.org/keywords/combinatorics","display_name":"Combinatorics","score":0.09853929281234741}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4696718156337738},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.4238005578517914},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.42167532444000244},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.4216492772102356},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.3690292239189148},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.34841692447662354},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3128083348274231},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.2081598937511444},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.18470358848571777},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1586504578590393},{"id":"https://openalex.org/C114614502","wikidata":"https://www.wikidata.org/wiki/Q76592","display_name":"Combinatorics","level":1,"score":0.09853929281234741},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2011.6044897","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2011.6044897","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2011 Proceedings of the ESSCIRC (ESSCIRC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.8799999952316284}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1998009542","https://openalex.org/W2033949796","https://openalex.org/W2072448041","https://openalex.org/W2122144284","https://openalex.org/W2128048972","https://openalex.org/W2129314919","https://openalex.org/W2151802820","https://openalex.org/W2178304595","https://openalex.org/W4236811439","https://openalex.org/W6682165497"],"related_works":["https://openalex.org/W2748952813","https://openalex.org/W3014521742","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W4306968100","https://openalex.org/W2171986175","https://openalex.org/W2089791793","https://openalex.org/W2038858740","https://openalex.org/W1491218245"],"abstract_inverted_index":{"Within-functional-block":[0],"fine-grained":[1,31],"adaptive":[2],"dual":[3],"supply":[4,32],"voltage":[5,33,59],"control":[6,35],"(FADVC)":[7],"is":[8,55],"proposed":[9,97],"to":[10,36,69,80],"reduce":[11],"the":[12,30,44,48,81,92,96,100,108],"power":[13,38,71,101],"of":[14,50],"CMOS":[15],"logic":[16],"circuits.":[17],"Both":[18,61],"process":[19],"and":[20,64,73],"design":[21],"variations":[22],"within":[23],"a":[24,51],"functional":[25],"block":[26],"are":[27,67],"compensated":[28],"by":[29,87,102],"(VDD)":[34],"minimize":[37],"at":[39,104],"fixed":[40],"clock":[41,106],"frequency.":[42],"In":[43],"40-nm":[45],"test":[46],"chips,":[47],"layout":[49],"data":[52],"encryption":[53],"core":[54],"divided":[56],"into":[57],"6\u00d77":[58],"domains.":[60],"high":[62],"VDD(VDDH)":[63],"low":[65],"VDD(VDDL)":[66],"supplied":[68],"each":[70],"domain":[72],"either":[74],"VDDHor":[75],"VDDLis":[76],"adaptively":[77],"selected":[78],"according":[79],"setup":[82],"error":[83],"warning":[84],"signals":[85],"generated":[86],"canary":[88],"flip-flops.":[89],"Compared":[90],"with":[91],"conventional":[93],"single":[94],"VDDoperation,":[95],"FADVC":[98],"reduced":[99],"12%":[103],"1-MHz":[105],"in":[107],"measurement.":[109]},"counts_by_year":[{"year":2021,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}