{"id":"https://openalex.org/W2150865404","doi":"https://doi.org/10.1109/esscirc.2010.5619756","title":"A loading effect insensitive and high precision clock synchronization circuit","display_name":"A loading effect insensitive and high precision clock synchronization circuit","publication_year":2010,"publication_date":"2010-09-01","ids":{"openalex":"https://openalex.org/W2150865404","doi":"https://doi.org/10.1109/esscirc.2010.5619756","mag":"2150865404"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2010.5619756","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2010.5619756","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Proceedings of ESSCIRC","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5053045810","display_name":"Kai\u2010Wei Hong","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":true,"raw_author_name":"Kai-Wei Hong","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101981427","display_name":"Kuo\u2010Hsing Cheng","orcid":"https://orcid.org/0000-0002-0997-5264"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Kuo-Hsing Cheng","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5024712282","display_name":"Chi-Hsiang Chen","orcid":null},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chi-Hsiang Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5025566121","display_name":"Jen\u2010Chieh Liu","orcid":"https://orcid.org/0000-0002-7045-6586"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Jen-Chieh Liu","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5101770112","display_name":"Chien\u2010Cheng Chen","orcid":"https://orcid.org/0000-0002-1684-4297"},"institutions":[{"id":"https://openalex.org/I22265921","display_name":"National Central University","ror":"https://ror.org/00944ve71","country_code":"TW","type":"education","lineage":["https://openalex.org/I22265921"]}],"countries":["TW"],"is_corresponding":false,"raw_author_name":"Chien-Cheng Chen","raw_affiliation_strings":["Department of Electrical Engineering, National Central University, Taiwan"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, National Central University, Taiwan","institution_ids":["https://openalex.org/I22265921"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5053045810"],"corresponding_institution_ids":["https://openalex.org/I22265921"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.16953972,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"3","issue":null,"first_page":"514","last_page":"517"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9976000189781189,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.989799976348877,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.8239092826843262},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.790727972984314},{"id":"https://openalex.org/keywords/cpu-multiplier","display_name":"CPU multiplier","score":0.7343592047691345},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.7300986051559448},{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.6748340129852295},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.6438048481941223},{"id":"https://openalex.org/keywords/clock-gating","display_name":"Clock gating","score":0.598568856716156},{"id":"https://openalex.org/keywords/clock-synchronization","display_name":"Clock synchronization","score":0.588097870349884},{"id":"https://openalex.org/keywords/clock-generator","display_name":"Clock generator","score":0.5786046981811523},{"id":"https://openalex.org/keywords/duty-cycle","display_name":"Duty cycle","score":0.5758815407752991},{"id":"https://openalex.org/keywords/chip","display_name":"Chip","score":0.563878059387207},{"id":"https://openalex.org/keywords/synchronization","display_name":"Synchronization (alternating current)","score":0.5397189259529114},{"id":"https://openalex.org/keywords/clock-drift","display_name":"Clock drift","score":0.5235602259635925},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.5204475522041321},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4489462077617645},{"id":"https://openalex.org/keywords/synchronizing","display_name":"Synchronizing","score":0.4483639895915985},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3877727687358856},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2970932126045227},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.24380871653556824},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.1836887001991272},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.11729958653450012},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.08366313576698303}],"concepts":[{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.8239092826843262},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.790727972984314},{"id":"https://openalex.org/C125576049","wikidata":"https://www.wikidata.org/wiki/Q2246273","display_name":"CPU multiplier","level":5,"score":0.7343592047691345},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.7300986051559448},{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.6748340129852295},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.6438048481941223},{"id":"https://openalex.org/C22716491","wikidata":"https://www.wikidata.org/wiki/Q590170","display_name":"Clock gating","level":5,"score":0.598568856716156},{"id":"https://openalex.org/C129891060","wikidata":"https://www.wikidata.org/wiki/Q1513059","display_name":"Clock synchronization","level":4,"score":0.588097870349884},{"id":"https://openalex.org/C2778023540","wikidata":"https://www.wikidata.org/wiki/Q2164847","display_name":"Clock generator","level":4,"score":0.5786046981811523},{"id":"https://openalex.org/C199822604","wikidata":"https://www.wikidata.org/wiki/Q557120","display_name":"Duty cycle","level":3,"score":0.5758815407752991},{"id":"https://openalex.org/C165005293","wikidata":"https://www.wikidata.org/wiki/Q1074500","display_name":"Chip","level":2,"score":0.563878059387207},{"id":"https://openalex.org/C2778562939","wikidata":"https://www.wikidata.org/wiki/Q1298791","display_name":"Synchronization (alternating current)","level":3,"score":0.5397189259529114},{"id":"https://openalex.org/C155837451","wikidata":"https://www.wikidata.org/wiki/Q1069144","display_name":"Clock drift","level":5,"score":0.5235602259635925},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.5204475522041321},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4489462077617645},{"id":"https://openalex.org/C162932704","wikidata":"https://www.wikidata.org/wiki/Q1058791","display_name":"Synchronizing","level":3,"score":0.4483639895915985},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3877727687358856},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2970932126045227},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.24380871653556824},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.1836887001991272},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.11729958653450012},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.08366313576698303}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2010.5619756","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2010.5619756","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2010 Proceedings of ESSCIRC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320321040","display_name":"National Science Council","ror":"https://ror.org/02kv4zf79"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":8,"referenced_works":["https://openalex.org/W1831473815","https://openalex.org/W1986547568","https://openalex.org/W2074806558","https://openalex.org/W2129435173","https://openalex.org/W2166287616","https://openalex.org/W2169622190","https://openalex.org/W2540774492","https://openalex.org/W6638798140"],"related_works":["https://openalex.org/W2169618112","https://openalex.org/W3006003651","https://openalex.org/W2224788396","https://openalex.org/W2205497670","https://openalex.org/W2125201667","https://openalex.org/W4313332229","https://openalex.org/W4231008241","https://openalex.org/W2286776167","https://openalex.org/W2386103431","https://openalex.org/W2139338465"],"abstract_inverted_index":{"This":[0,23],"study":[1],"proposes":[2],"a":[3,63,124,147],"output":[4,96,107],"loading":[5],"effect":[6,94],"insensitive":[7],"and":[8,32,58,91,120,153,171,177],"high":[9],"precision":[10],"clock":[11,21,31,35,38,52,57,61,84,119,122],"synchronization":[12],"(HPCS)":[13],"circuit":[14],"which":[15],"can":[16,48,112],"accept":[17],"variable":[18],"duty":[19,79],"cycle":[20,80],"signal.":[22,85],"HPCS":[24,47,73,88,111],"is":[25,136,144,187],"capable":[26],"of":[27,95,184],"synchronizing":[28],"the":[29,33,45,51,55,59,68,72,87,93,101,106,110,114,117,131,168],"external":[30,56,118],"internal":[34,60,121],"in":[36,62,146],"3":[37],"cycles.":[39],"By":[40],"using":[41],"three":[42],"innovative":[43],"techniques,":[44],"proposed":[46,142],"also":[49],"reduce":[50],"skew":[53],"between":[54,116],"chip.":[64],"First,":[65],"by":[66,99],"modifying":[67],"mirror":[69],"control":[70],"circuit,":[71],"operates":[74],"correctly":[75],"with":[76,123],"an":[77,155],"arbitrary":[78],"(25%":[81],"~":[82],"75%)":[83],"Second,":[86],"works":[89],"precisely":[90],"ignores":[92],"load":[97],"changes":[98],"moving":[100],"measurement":[102],"delay":[103],"line":[104],"beyond":[105],"driver.":[108],"Finally,":[109],"enhance":[113],"resolution":[115],"fine":[125],"tuning":[126],"structure.":[127],"After":[128],"phase":[129,134],"locking,":[130],"maximum":[132],"static":[133],"error":[135],"less":[137],"than":[138],"20":[139],"ps.":[140],"The":[141,181],"chip":[143,186],"fabricated":[145],"TSMC":[148],"130":[149],"nm":[150],"CMOS":[151],"process,":[152],"has":[154],"operating":[156],"frequency":[157],"range":[158],"from":[159],"300":[160],"MHz":[161],"to":[162],"600":[163,166],"MHz.":[164],"At":[165],"MHz,":[167],"power":[169],"consumption":[170],"rms":[172],"jitter":[173],"are":[174],"2.4":[175],"mW":[176],"3.06":[178],"ps,":[179],"respectively.":[180],"active":[182],"area":[183],"this":[185],"0.3\u00d70.13":[188],"mm":[189],"<sup":[190],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[191],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[192],".":[193]},"counts_by_year":[{"year":2023,"cited_by_count":1},{"year":2015,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
