{"id":"https://openalex.org/W2042646147","doi":"https://doi.org/10.1109/esscirc.2009.5326010","title":"647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA","display_name":"647 MHz, 0.642pJ/block/cycle 65nm self synchronous FPGA","publication_year":2009,"publication_date":"2009-09-01","ids":{"openalex":"https://openalex.org/W2042646147","doi":"https://doi.org/10.1109/esscirc.2009.5326010","mag":"2042646147"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2009.5326010","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2009.5326010","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Proceedings of ESSCIRC","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5085875405","display_name":"Benjamin Devlin","orcid":"https://orcid.org/0009-0008-2823-549X"},"institutions":[{"id":"https://openalex.org/I153327471","display_name":"Bunkyo University","ror":"https://ror.org/053h75930","country_code":"JP","type":"education","lineage":["https://openalex.org/I153327471"]},{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Benjamin Devlin","raw_affiliation_strings":["Dept. of Electronic Engineering, University of Tokyo, Bunkyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Dept. of Electronic Engineering, University of Tokyo, Bunkyo, Japan","institution_ids":["https://openalex.org/I153327471","https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5035293063","display_name":"MyeongGyu Jeong","orcid":null},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Jeong MyeongGyu","raw_affiliation_strings":["Tokyo Daigaku, Bunkyo-ku, Tokyo, JP"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Tokyo Daigaku, Bunkyo-ku, Tokyo, JP","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5071803491","display_name":"Toru Nakura","orcid":"https://orcid.org/0000-0001-5945-3918"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toru Nakura","raw_affiliation_strings":["VLSI Design and Education Center(VDEC), University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center(VDEC), University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5102900006","display_name":"Makoto Ikeda","orcid":"https://orcid.org/0000-0002-6644-4224"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Makoto Ikeda","raw_affiliation_strings":["VLSI Design and Education Center(VDEC), University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center(VDEC), University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5028680447","display_name":"Kunihiro Asada","orcid":"https://orcid.org/0000-0002-1150-0241"},"institutions":[{"id":"https://openalex.org/I74801974","display_name":"The University of Tokyo","ror":"https://ror.org/057zh3y96","country_code":"JP","type":"education","lineage":["https://openalex.org/I74801974"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kunihiro Asada","raw_affiliation_strings":["VLSI Design and Education Center(VDEC), University of Tokyo, Tokyo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"VLSI Design and Education Center(VDEC), University of Tokyo, Tokyo, Japan","institution_ids":["https://openalex.org/I74801974"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":6,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"156","last_page":"159"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/logic-block","display_name":"Logic block","score":0.7627103328704834},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.6675261855125427},{"id":"https://openalex.org/keywords/block","display_name":"Block (permutation group theory)","score":0.6652979850769043},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6495740413665771},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5762357711791992},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.5584161281585693},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.4702025055885315},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.45728346705436707},{"id":"https://openalex.org/keywords/gate-array","display_name":"Gate array","score":0.44235795736312866},{"id":"https://openalex.org/keywords/programmable-logic-array","display_name":"Programmable logic array","score":0.4365469813346863},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.4228641986846924},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.39300549030303955},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.37434566020965576},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.2712988257408142},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.20277613401412964},{"id":"https://openalex.org/keywords/algorithm","display_name":"Algorithm","score":0.15554338693618774},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.09669536352157593}],"concepts":[{"id":"https://openalex.org/C2778325283","wikidata":"https://www.wikidata.org/wiki/Q1125244","display_name":"Logic block","level":3,"score":0.7627103328704834},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.6675261855125427},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.6652979850769043},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6495740413665771},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5762357711791992},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.5584161281585693},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.4702025055885315},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.45728346705436707},{"id":"https://openalex.org/C114237110","wikidata":"https://www.wikidata.org/wiki/Q114901","display_name":"Gate array","level":3,"score":0.44235795736312866},{"id":"https://openalex.org/C182322920","wikidata":"https://www.wikidata.org/wiki/Q2112217","display_name":"Programmable logic array","level":3,"score":0.4365469813346863},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.4228641986846924},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.39300549030303955},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.37434566020965576},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.2712988257408142},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.20277613401412964},{"id":"https://openalex.org/C11413529","wikidata":"https://www.wikidata.org/wiki/Q8366","display_name":"Algorithm","level":1,"score":0.15554338693618774},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.09669536352157593},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C2524010","wikidata":"https://www.wikidata.org/wiki/Q8087","display_name":"Geometry","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2009.5326010","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2009.5326010","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2009 Proceedings of ESSCIRC","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7300000190734863,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[{"id":"https://openalex.org/F4320322832","display_name":"University of Tokyo","ror":"https://ror.org/057zh3y96"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1514480347","https://openalex.org/W2117956094","https://openalex.org/W2123222669","https://openalex.org/W2128723913","https://openalex.org/W2128876494","https://openalex.org/W2137443761","https://openalex.org/W2138840350","https://openalex.org/W2156662023","https://openalex.org/W2164337590","https://openalex.org/W6630761995"],"related_works":["https://openalex.org/W3023652529","https://openalex.org/W2188536820","https://openalex.org/W2182398074","https://openalex.org/W2071567894","https://openalex.org/W2480852620","https://openalex.org/W2246445978","https://openalex.org/W2121539644","https://openalex.org/W2788600543","https://openalex.org/W2070538238","https://openalex.org/W4235216035"],"abstract_inverted_index":{"We":[0],"propose":[1],"a":[2,28,88,100],"self":[3,22,40],"synchronous":[4,23,41],"field":[5],"programmable":[6],"gate":[7],"array":[8],"(SSFPGA)":[9],"with":[10,33,55,71],"dual-pipeline":[11],"(DP)":[12],"architecture":[13],"to":[14],"eliminate":[15],"pre-charge":[16],"time":[17],"for":[18,37,87,99],"dynamic":[19],"logic.":[20],"A":[21,39],"LUT":[24],"(SSLUT)":[25],"consists":[26,45],"of":[27,46,90],"three":[29],"input":[30],"tree-type":[31],"structure":[32],"8":[34],"bit":[35,102],"SRAM":[36],"programming.":[38],"switch":[42],"box":[43],"(SSSB)":[44],"both":[47],"pass":[48],"transistors":[49],"and":[50,58,67,77,96],"buffers.":[51],"One":[52],"common":[53],"block":[54],"one":[56,59],"SSLUT":[57],"SSSB":[60],"occupies":[61],"2.2\u03bb":[62],"<sup":[63],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[64],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">2</sup>":[65],"area":[66],"the":[68],"prototype":[69],"SSFPGA":[70],"34x30":[72],"(1020)":[73],"blocks":[74],"is":[75],"designed":[76],"fabricated":[78],"using":[79],"65nm":[80],"CMOS.":[81],"Measured":[82],"results":[83,107],"show":[84,108],"647MHz":[85],"operation":[86,98,110],"chain":[89],"32":[91],"AND":[92],"gates":[93],"at":[94,111],"1.2V":[95],"430MHz":[97],"3":[101],"ripple":[103],"carry":[104],"adder.":[105],"Simulation":[106],"0.642pJ/block/cycle":[109],"647MHz,":[112],"1.2V.":[113]},"counts_by_year":[{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}