{"id":"https://openalex.org/W2148201276","doi":"https://doi.org/10.1109/esscirc.2008.4681850","title":"Current reuse CMOS LNA for UWB applications","display_name":"Current reuse CMOS LNA for UWB applications","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2148201276","doi":"https://doi.org/10.1109/esscirc.2008.4681850","mag":"2148201276"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2008.4681850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2008.4681850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2008 - 34th European Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110526008","display_name":"Thierry Taris","orcid":null},"institutions":[{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"T. Taris","raw_affiliation_strings":["IMS laboratory, Talence, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMS laboratory, Talence, France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068662659","display_name":"Yann Deval","orcid":"https://orcid.org/0000-0002-7358-8904"},"institutions":[{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"Y. Deval","raw_affiliation_strings":["IMS laboratory, Talence, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMS laboratory, Talence, France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5057940221","display_name":"J.B. B\u00e9gueret","orcid":"https://orcid.org/0000-0003-3245-4640"},"institutions":[{"id":"https://openalex.org/I4210157089","display_name":"Laboratoire de l'Int\u00e9gration du Mat\u00e9riau au Syst\u00e8me","ror":"https://ror.org/04nabhy78","country_code":"FR","type":"facility","lineage":["https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I15057530","https://openalex.org/I4210091158","https://openalex.org/I4210095849","https://openalex.org/I4210157089","https://openalex.org/I4210160189"]},{"id":"https://openalex.org/I4210160189","display_name":"Institut Polytechnique de Bordeaux","ror":"https://ror.org/054qv7y42","country_code":"FR","type":"education","lineage":["https://openalex.org/I4210160189"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"J.B. Begueret","raw_affiliation_strings":["IMS laboratory, Talence, France"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"IMS laboratory, Talence, France","institution_ids":["https://openalex.org/I4210157089","https://openalex.org/I4210160189"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":2,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":4.2699,"has_fulltext":false,"cited_by_count":17,"citation_normalized_percentile":{"value":0.95175129,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":"rfic 2006","issue":null,"first_page":"294","last_page":"297"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10262","display_name":"Microwave Engineering and Waveguides","score":0.9991999864578247,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12024","display_name":"Ultra-Wideband Communications Technology","score":0.9968000054359436,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.790375828742981},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.6420928239822388},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.5371089577674866},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5232511758804321},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.46633005142211914},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.4416835904121399},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4360713064670563},{"id":"https://openalex.org/keywords/integrated-circuit-design","display_name":"Integrated circuit design","score":0.41896504163742065},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.3942822813987732},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.29627496004104614},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.26139408349990845},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.23486050963401794},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.17094063758850098}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.790375828742981},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.6420928239822388},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.5371089577674866},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5232511758804321},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.46633005142211914},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.4416835904121399},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4360713064670563},{"id":"https://openalex.org/C74524168","wikidata":"https://www.wikidata.org/wiki/Q1074539","display_name":"Integrated circuit design","level":2,"score":0.41896504163742065},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.3942822813987732},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.29627496004104614},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.26139408349990845},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.23486050963401794},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.17094063758850098},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2008.4681850","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2008.4681850","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2008 - 34th European Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7","score":0.6600000262260437}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":15,"referenced_works":["https://openalex.org/W618610266","https://openalex.org/W1518120160","https://openalex.org/W1734402927","https://openalex.org/W1976697859","https://openalex.org/W2044076010","https://openalex.org/W2061353119","https://openalex.org/W2065707837","https://openalex.org/W2118196851","https://openalex.org/W2120983426","https://openalex.org/W2137083705","https://openalex.org/W2138407882","https://openalex.org/W2160739102","https://openalex.org/W2173757524","https://openalex.org/W6637886799","https://openalex.org/W6680389796"],"related_works":["https://openalex.org/W3014521742","https://openalex.org/W2617868873","https://openalex.org/W3204141294","https://openalex.org/W4386230336","https://openalex.org/W4306968100","https://openalex.org/W2171986175","https://openalex.org/W2389800961","https://openalex.org/W1995389502","https://openalex.org/W2070694218","https://openalex.org/W2532822217"],"abstract_inverted_index":{"To":[0],"comply":[1],"with":[2],"the":[3,82,116,137,142],"low":[4,6],"power":[5],"voltage":[7,38],"design":[8],"constrains":[9],"in":[10,23,71],"modern":[11],"RF":[12],"CMOS":[13,28],"technologies,":[14],"a":[15,24,34,56,62,72,89,95,99,107,121,153],"new":[16],"LNA":[17,80,129],"topology":[18],"is":[19,68,131],"here":[20],"proposed.":[21],"Implemented":[22],"standard":[25],"130":[26],"nm":[27],"technology,":[29],"two":[30],"circuits":[31,105],"operating":[32],"under":[33,133],"1.4":[35],"V":[36],"nominal":[37],"are":[39],"reported.":[40],"The":[41,78],"first":[42],"one":[43],"dedicated":[44],"to":[45,74,141,149],"lower":[46],"band":[47],"of":[48],"European":[49],"UWB":[50],"allocation":[51],"-i.e.":[52],"3-5":[53],"GHz-":[54],"achieves":[55],"13.8":[57],"dB":[58,76,91,97,111,123],"maximum":[59,92],"gain":[60,93],"for":[61],"5.8":[63],"mA":[64,101],"current":[65,102],"consumption.":[66,103],"NF":[67],"so":[69],"included":[70,151],"4.2":[73],"6.1":[75],"range.":[77],"second":[79],"addresses":[81],"6-10":[83],"GHz":[84],"upper":[85],"band.":[86],"It":[87],"performs":[88],"12.2":[90],"and":[94,124],"4.5":[96],"NFminfor":[98],"3":[100],"Both":[104],"exhibit":[106],"more":[108],"than":[109],"-10":[110],"input":[112,138],"return":[113],"loss":[114],"over":[115],"considered":[117],"bandwidth.":[118],"S21even":[119],"reaches":[120],"9":[122],"11":[125],"dB,":[126],"respectively,":[127],"when":[128],"core":[130],"supplied":[132],"0.9":[134],"V.":[135],"Matching":[136],"network":[139],"order":[140],"addressed":[143],"bandwidth":[144],"affords":[145],"each":[146],"circuit":[147],"implementation":[148],"be":[150],"within":[152],"1.8":[154],"mm2silicon":[155],"area.":[156]},"counts_by_year":[{"year":2021,"cited_by_count":2},{"year":2020,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-07-29T14:22:42.915294","created_date":"2025-10-10T00:00:00"}