{"id":"https://openalex.org/W2132636601","doi":"https://doi.org/10.1109/esscirc.2008.4681825","title":"A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network","display_name":"A 5.2Gb/p/s GDDR5 SDRAM with CML clock distribution network","publication_year":2008,"publication_date":"2008-09-01","ids":{"openalex":"https://openalex.org/W2132636601","doi":"https://doi.org/10.1109/esscirc.2008.4681825","mag":"2132636601"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2008.4681825","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2008.4681825","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2008 - 34th European Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052695892","display_name":"Kyung-Hoon Kim","orcid":"https://orcid.org/0000-0003-3925-8917"},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":true,"raw_author_name":"KyungHoon Kim","raw_affiliation_strings":["Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","Memory R&D, Hynix Semicond. Inc., Ichon"],"affiliations":[{"raw_affiliation_string":"Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Memory R&D, Hynix Semicond. Inc., Ichon","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5066003460","display_name":"Sang-Sic Yoon","orcid":null},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"SangSic Yoon","raw_affiliation_strings":["Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","Memory R&D, Hynix Semicond. Inc., Ichon"],"affiliations":[{"raw_affiliation_string":"Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Memory R&D, Hynix Semicond. Inc., Ichon","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5005029791","display_name":"Ki-Chang Kwean","orcid":null},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"KiChang Kwean","raw_affiliation_strings":["Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","Memory R&D, Hynix Semicond. Inc., Ichon"],"affiliations":[{"raw_affiliation_string":"Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Memory R&D, Hynix Semicond. Inc., Ichon","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074082712","display_name":"Daehan Kwon","orcid":"https://orcid.org/0000-0002-2033-8928"},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"DaeHan Kwon","raw_affiliation_strings":["Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","Memory R&D, Hynix Semicond. Inc., Ichon"],"affiliations":[{"raw_affiliation_string":"Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Memory R&D, Hynix Semicond. Inc., Ichon","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"middle","author":{"id":null,"display_name":"SunSuk Yang","orcid":null},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"SunSuk Yang","raw_affiliation_strings":["Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","Memory R&D, Hynix Semicond. Inc., Ichon"],"affiliations":[{"raw_affiliation_string":"Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Memory R&D, Hynix Semicond. Inc., Ichon","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5020869648","display_name":"M. Park","orcid":null},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"MunPhil Park","raw_affiliation_strings":["Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","Memory R&D, Hynix Semicond. Inc., Ichon"],"affiliations":[{"raw_affiliation_string":"Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Memory R&D, Hynix Semicond. Inc., Ichon","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101920248","display_name":"Yong-Ki Kim","orcid":"https://orcid.org/0000-0002-8646-0758"},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"YongKi Kim","raw_affiliation_strings":["Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","Memory R&D, Hynix Semicond. Inc., Ichon"],"affiliations":[{"raw_affiliation_string":"Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Memory R&D, Hynix Semicond. Inc., Ichon","institution_ids":["https://openalex.org/I10654025"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5037950533","display_name":"Byong-Tae Chung","orcid":null},"institutions":[{"id":"https://openalex.org/I10654025","display_name":"SK Group (United States)","ror":"https://ror.org/00qajw440","country_code":"US","type":"company","lineage":["https://openalex.org/I10654025","https://openalex.org/I134353371"]},{"id":"https://openalex.org/I134353371","display_name":"SK Group (South Korea)","ror":"https://ror.org/03696td91","country_code":"KR","type":"company","lineage":["https://openalex.org/I134353371"]}],"countries":["KR","US"],"is_corresponding":false,"raw_author_name":"ByongTae Chung","raw_affiliation_strings":["Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","Memory R&D, Hynix Semicond. Inc., Ichon"],"affiliations":[{"raw_affiliation_string":"Design Team, Memory Research & Development, Hynix Semiconductor, Inc., Ichon, South Korea","institution_ids":["https://openalex.org/I134353371"]},{"raw_affiliation_string":"Memory R&D, Hynix Semicond. Inc., Ichon","institution_ids":["https://openalex.org/I10654025"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":8,"corresponding_author_ids":["https://openalex.org/A5052695892"],"corresponding_institution_ids":["https://openalex.org/I10654025","https://openalex.org/I134353371"],"apc_list":null,"apc_paid":null,"fwci":0.678,"has_fulltext":false,"cited_by_count":3,"citation_normalized_percentile":{"value":0.74426611,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"194","last_page":"197"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11417","display_name":"Advancements in PLL and VCO Technologies","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11444","display_name":"Electromagnetic Compatibility and Noise Suppression","score":0.9983999729156494,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/jitter","display_name":"Jitter","score":0.8048462271690369},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6566728353500366},{"id":"https://openalex.org/keywords/dram","display_name":"Dram","score":0.6546908020973206},{"id":"https://openalex.org/keywords/cas-latency","display_name":"CAS latency","score":0.5669234991073608},{"id":"https://openalex.org/keywords/digital-clock-manager","display_name":"Digital clock manager","score":0.5104454755783081},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4973049461841583},{"id":"https://openalex.org/keywords/clock-domain-crossing","display_name":"Clock domain crossing","score":0.48734578490257263},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.4261187016963959},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.41741180419921875},{"id":"https://openalex.org/keywords/memory-controller","display_name":"Memory controller","score":0.28861942887306213},{"id":"https://openalex.org/keywords/clock-skew","display_name":"Clock skew","score":0.2580724358558655},{"id":"https://openalex.org/keywords/computer-network","display_name":"Computer network","score":0.2555702328681946},{"id":"https://openalex.org/keywords/clock-signal","display_name":"Clock signal","score":0.2427632212638855},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.16176599264144897},{"id":"https://openalex.org/keywords/synchronous-circuit","display_name":"Synchronous circuit","score":0.1584029197692871},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.11511734127998352}],"concepts":[{"id":"https://openalex.org/C134652429","wikidata":"https://www.wikidata.org/wiki/Q1052698","display_name":"Jitter","level":2,"score":0.8048462271690369},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6566728353500366},{"id":"https://openalex.org/C7366592","wikidata":"https://www.wikidata.org/wiki/Q1255620","display_name":"Dram","level":2,"score":0.6546908020973206},{"id":"https://openalex.org/C189930140","wikidata":"https://www.wikidata.org/wiki/Q1112878","display_name":"CAS latency","level":4,"score":0.5669234991073608},{"id":"https://openalex.org/C113074038","wikidata":"https://www.wikidata.org/wiki/Q5276052","display_name":"Digital clock manager","level":5,"score":0.5104454755783081},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4973049461841583},{"id":"https://openalex.org/C127204226","wikidata":"https://www.wikidata.org/wiki/Q5134799","display_name":"Clock domain crossing","level":5,"score":0.48734578490257263},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.4261187016963959},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.41741180419921875},{"id":"https://openalex.org/C100800780","wikidata":"https://www.wikidata.org/wiki/Q1175867","display_name":"Memory controller","level":3,"score":0.28861942887306213},{"id":"https://openalex.org/C60501442","wikidata":"https://www.wikidata.org/wiki/Q4382014","display_name":"Clock skew","level":4,"score":0.2580724358558655},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.2555702328681946},{"id":"https://openalex.org/C137059387","wikidata":"https://www.wikidata.org/wiki/Q426882","display_name":"Clock signal","level":3,"score":0.2427632212638855},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.16176599264144897},{"id":"https://openalex.org/C42196554","wikidata":"https://www.wikidata.org/wiki/Q1186179","display_name":"Synchronous circuit","level":4,"score":0.1584029197692871},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.11511734127998352}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2008.4681825","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2008.4681825","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2008 - 34th European Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5099999904632568}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":3,"referenced_works":["https://openalex.org/W2102284281","https://openalex.org/W2141825982","https://openalex.org/W2788706082"],"related_works":["https://openalex.org/W2094329012","https://openalex.org/W4293430534","https://openalex.org/W2342813629","https://openalex.org/W3150934690","https://openalex.org/W4297812927","https://openalex.org/W2335743642","https://openalex.org/W2035322460","https://openalex.org/W1574257586","https://openalex.org/W2384124522","https://openalex.org/W2370061661"],"abstract_inverted_index":{"A":[0],"1":[1],"Gb":[2],"density,":[3],"5.2":[4],"Gbps/s/pin":[5],"data":[6,50],"rate":[7],"GDDR5":[8],"SDRAM":[9],"was":[10],"developed":[11],"using":[12,42],"66":[13],"nm":[14],"DRAM":[15],"process.":[16],"It":[17],"uses":[18],"traditional":[19],"Core":[20],"architecture,":[21],"8-bit":[22],"pre-fetch":[23],"with":[24],"16-banks,":[25],"but":[26],"the":[27,53],"clocking":[28,65],"and":[29],"interface":[30],"topology":[31],"are":[32],"fully":[33],"changed":[34],"for":[35],"operating":[36],"more":[37],"than":[38],"4":[39],"Gbps":[40],"without":[41],"differential":[43],"signaling.":[44],"Major":[45],"barrier":[46],"to":[47],"achieving":[48],"high":[49],"bandwidth":[51],"is":[52],"clock":[54],"jitter.":[55],"To":[56],"overcome":[57],"this":[58,60],"limitation,":[59],"project":[61],"utilizes":[62],"a":[63],"CML":[64],"scheme.":[66]},"counts_by_year":[{"year":2013,"cited_by_count":1}],"updated_date":"2026-04-17T18:11:37.981687","created_date":"2025-10-10T00:00:00"}