{"id":"https://openalex.org/W2109047165","doi":"https://doi.org/10.1109/esscirc.2007.4430307","title":"A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48&amp;#x00D7;42b 1R/1W programmable register file in 65nm CMOS","display_name":"A 200mV to 1.2V, 4.4MHz to 6.3GHz, 48&amp;#x00D7;42b 1R/1W programmable register file in 65nm CMOS","publication_year":2007,"publication_date":"2007-09-01","ids":{"openalex":"https://openalex.org/W2109047165","doi":"https://doi.org/10.1109/esscirc.2007.4430307","mag":"2109047165"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2007.4430307","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2007.4430307","pdf_url":null,"source":{"id":"https://openalex.org/S4210191203","display_name":"Proceedings of ESSCIRC","issn_l":"1930-8833","issn":["1930-8833","2643-1319"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5006348328","display_name":"Amit Agarwal","orcid":"https://orcid.org/0000-0002-4220-3346"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Amit Agarwal","raw_affiliation_strings":["Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012819177","display_name":"Nilanjan Banerjee","orcid":"https://orcid.org/0000-0003-4466-0898"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Nilanjan Banerjee","raw_affiliation_strings":["Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5109275074","display_name":"Steven K. Hsu","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Steven K. Hsu","raw_affiliation_strings":["Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Ram K. Krishnamurthy","raw_affiliation_strings":["Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA"],"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5046257293","display_name":"Kaushik Roy","orcid":"https://orcid.org/0000-0003-4937-2115"},"institutions":[{"id":"https://openalex.org/I219193219","display_name":"Purdue University West Lafayette","ror":"https://ror.org/02dqehb95","country_code":"US","type":"education","lineage":["https://openalex.org/I219193219"]},{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Kaushik Roy","raw_affiliation_strings":["Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","Purdue University, West Lafayette, IN, USA"],"affiliations":[{"raw_affiliation_string":"Circuit Research Laboratories, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]},{"raw_affiliation_string":"Purdue University, West Lafayette, IN, USA","institution_ids":["https://openalex.org/I219193219"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":["https://openalex.org/A5006348328"],"corresponding_institution_ids":["https://openalex.org/I1343180700"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.14656352,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"316","last_page":"319"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/register-file","display_name":"Register file","score":0.7659178972244263},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7180135250091553},{"id":"https://openalex.org/keywords/stacking","display_name":"Stacking","score":0.7174540162086487},{"id":"https://openalex.org/keywords/porting","display_name":"Porting","score":0.6079789400100708},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5563044548034668},{"id":"https://openalex.org/keywords/register","display_name":"Register (sociolinguistics)","score":0.5375949740409851},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.48621001839637756},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4775072932243347},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.329667329788208},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.32306843996047974},{"id":"https://openalex.org/keywords/computer-hardware","display_name":"Computer hardware","score":0.31005486845970154},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.2539186477661133},{"id":"https://openalex.org/keywords/instruction-set","display_name":"Instruction set","score":0.0773056149482727}],"concepts":[{"id":"https://openalex.org/C117280010","wikidata":"https://www.wikidata.org/wiki/Q180944","display_name":"Register file","level":3,"score":0.7659178972244263},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7180135250091553},{"id":"https://openalex.org/C33347731","wikidata":"https://www.wikidata.org/wiki/Q285210","display_name":"Stacking","level":2,"score":0.7174540162086487},{"id":"https://openalex.org/C106251023","wikidata":"https://www.wikidata.org/wiki/Q851989","display_name":"Porting","level":3,"score":0.6079789400100708},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5563044548034668},{"id":"https://openalex.org/C2779235478","wikidata":"https://www.wikidata.org/wiki/Q286576","display_name":"Register (sociolinguistics)","level":2,"score":0.5375949740409851},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.48621001839637756},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4775072932243347},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.329667329788208},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.32306843996047974},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.31005486845970154},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.2539186477661133},{"id":"https://openalex.org/C202491316","wikidata":"https://www.wikidata.org/wiki/Q272683","display_name":"Instruction set","level":2,"score":0.0773056149482727},{"id":"https://openalex.org/C2777904410","wikidata":"https://www.wikidata.org/wiki/Q7397","display_name":"Software","level":2,"score":0.0},{"id":"https://openalex.org/C138885662","wikidata":"https://www.wikidata.org/wiki/Q5891","display_name":"Philosophy","level":0,"score":0.0},{"id":"https://openalex.org/C41895202","wikidata":"https://www.wikidata.org/wiki/Q8162","display_name":"Linguistics","level":1,"score":0.0},{"id":"https://openalex.org/C46141821","wikidata":"https://www.wikidata.org/wiki/Q209402","display_name":"Nuclear magnetic resonance","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2007.4430307","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2007.4430307","pdf_url":null,"source":{"id":"https://openalex.org/S4210191203","display_name":"Proceedings of ESSCIRC","issn_l":"1930-8833","issn":["1930-8833","2643-1319"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8700000047683716,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1550639219","https://openalex.org/W2051743745","https://openalex.org/W2144289559","https://openalex.org/W2158705165","https://openalex.org/W6683521617"],"related_works":["https://openalex.org/W2356602486","https://openalex.org/W2351992668","https://openalex.org/W2324828474","https://openalex.org/W2374315191","https://openalex.org/W2391207559","https://openalex.org/W2384715785","https://openalex.org/W2349624418","https://openalex.org/W2064459023","https://openalex.org/W2483419948","https://openalex.org/W4394246196"],"abstract_inverted_index":{"This":[0],"paper":[1],"describes":[2],"a":[3],"48times42b":[4],"1-read,":[5],"1-write":[6],"ported":[7],"register":[8,47],"file":[9],"which":[10,45],"operates":[11],"at":[12,51,64],"supply":[13,54,66],"voltage":[14],"range":[15],"of":[16],"1.2":[17],"V":[18,26],"(6.1-6.3":[19],"GHz,":[20],"47":[21],"mW)":[22,30],"down":[23],"to":[24,49,61],"0.2":[25],"(4-4.4":[27],"MHz,":[28],"0.01":[29],"in":[31],"65":[32],"nm":[33],"CMOS.":[34],"Two":[35],"programmable":[36],"techniques,":[37],"triple":[38],"stacking":[39,42],"and":[40],"forced":[41],"are":[43],"proposed":[44],"enable":[46],"files":[48],"operate":[50],"ultra":[52],"low":[53],"voltages":[55],"while":[56],"maintaining":[57],"the":[58],"performance":[59],"comparable":[60],"conventional":[62],"design":[63],"high":[65],"voltages.":[67]},"counts_by_year":[{"year":2019,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
