{"id":"https://openalex.org/W2115970471","doi":"https://doi.org/10.1109/esscirc.2007.4430304","title":"Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept","display_name":"Ultra low power subthreshold MOS current mode logic circuits using a novel load device concept","publication_year":2007,"publication_date":"2007-09-01","ids":{"openalex":"https://openalex.org/W2115970471","doi":"https://doi.org/10.1109/esscirc.2007.4430304","mag":"2115970471"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2007.4430304","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2007.4430304","pdf_url":null,"source":{"id":"https://openalex.org/S4210191203","display_name":"Proceedings of ESSCIRC","issn_l":"1930-8833","issn":["1930-8833","2643-1319"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":true,"oa_status":"green","oa_url":"http://infoscience.epfl.ch/record/109175","any_repository_has_fulltext":true},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5052867620","display_name":"Armin Tajalli","orcid":"https://orcid.org/0000-0002-0222-3561"},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":true,"raw_author_name":"Armin Tajalli","raw_affiliation_strings":["Microelectronic Systems Laboratory (LSM), Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Lausanne"],"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory (LSM), Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Lausanne","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072178473","display_name":"Eric A. Vittoz","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Eric Vittoz","raw_affiliation_strings":["Microelectronic Systems Laboratory (LSM), Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Lausanne"],"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory (LSM), Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Lausanne","institution_ids":[]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072423303","display_name":"Yusuf Leblebici","orcid":null},"institutions":[{"id":"https://openalex.org/I5124864","display_name":"\u00c9cole Polytechnique F\u00e9d\u00e9rale de Lausanne","ror":"https://ror.org/02s376052","country_code":"CH","type":"education","lineage":["https://openalex.org/I2799323385","https://openalex.org/I5124864"]}],"countries":["CH"],"is_corresponding":false,"raw_author_name":"Yusuf Leblebici","raw_affiliation_strings":["Microelectronic Systems Laboratory (LSM), Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","Microelectron. Syst. Lab., Lausanne"],"affiliations":[{"raw_affiliation_string":"Microelectronic Systems Laboratory (LSM), Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne, Lausanne, Switzerland","institution_ids":["https://openalex.org/I5124864"]},{"raw_affiliation_string":"Microelectron. Syst. Lab., Lausanne","institution_ids":[]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5110250651","display_name":"E.J. Brauer","orcid":null},"institutions":[{"id":"https://openalex.org/I203172682","display_name":"Northern Arizona University","ror":"https://ror.org/0272j5188","country_code":"US","type":"education","lineage":["https://openalex.org/I203172682"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Elizabeth J. Brauer","raw_affiliation_strings":["Department of Electrical Engineering, Northern Arizona University, Flagstaff, AZ, USA","Department of Electrical Engineering, Northern Arizona University, Flagstaff, 86011 USA"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Northern Arizona University, Flagstaff, AZ, USA","institution_ids":["https://openalex.org/I203172682"]},{"raw_affiliation_string":"Department of Electrical Engineering, Northern Arizona University, Flagstaff, 86011 USA","institution_ids":["https://openalex.org/I203172682"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":4,"corresponding_author_ids":["https://openalex.org/A5052867620"],"corresponding_institution_ids":["https://openalex.org/I5124864"],"apc_list":null,"apc_paid":null,"fwci":5.6199,"has_fulltext":false,"cited_by_count":33,"citation_normalized_percentile":{"value":0.96013529,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"304","last_page":"307"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.8554499745368958},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.7758140563964844},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.7204725742340088},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7187366485595703},{"id":"https://openalex.org/keywords/current-mode-logic","display_name":"Current-mode logic","score":0.6081491708755493},{"id":"https://openalex.org/keywords/triode","display_name":"Triode","score":0.5953317284584045},{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.5790752172470093},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5747721791267395},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5166340470314026},{"id":"https://openalex.org/keywords/power\u2013delay-product","display_name":"Power\u2013delay product","score":0.47647807002067566},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4729944169521332},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.4533025026321411},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.4371917247772217},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.4249695837497711},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.37137752771377563},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3581673502922058},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.2844259738922119},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.280786395072937},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.28077197074890137},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.1402512490749359},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.08377805352210999},{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.08331188559532166},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.07154446840286255}],"concepts":[{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.8554499745368958},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.7758140563964844},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.7204725742340088},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7187366485595703},{"id":"https://openalex.org/C2780295579","wikidata":"https://www.wikidata.org/wiki/Q5195108","display_name":"Current-mode logic","level":3,"score":0.6081491708755493},{"id":"https://openalex.org/C123544296","wikidata":"https://www.wikidata.org/wiki/Q176129","display_name":"Triode","level":4,"score":0.5953317284584045},{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.5790752172470093},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5747721791267395},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5166340470314026},{"id":"https://openalex.org/C2776391166","wikidata":"https://www.wikidata.org/wiki/Q7236873","display_name":"Power\u2013delay product","level":4,"score":0.47647807002067566},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4729944169521332},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.4533025026321411},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.4371917247772217},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.4249695837497711},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.37137752771377563},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3581673502922058},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.2844259738922119},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.280786395072937},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.28077197074890137},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.1402512490749359},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.08377805352210999},{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.08331188559532166},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.07154446840286255},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/esscirc.2007.4430304","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2007.4430304","pdf_url":null,"source":{"id":"https://openalex.org/S4210191203","display_name":"Proceedings of ESSCIRC","issn_l":"1930-8833","issn":["1930-8833","2643-1319"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","raw_type":"proceedings-article"},{"id":"pmh:oai:infoscience.epfl.ch:109175","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/109175","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"}],"best_oa_location":{"id":"pmh:oai:infoscience.epfl.ch:109175","is_oa":true,"landing_page_url":"http://infoscience.epfl.ch/record/109175","pdf_url":null,"source":{"id":"https://openalex.org/S4306400487","display_name":"Infoscience (Ecole Polytechnique F\u00e9d\u00e9rale de Lausanne)","issn_l":null,"issn":null,"is_oa":true,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Text"},"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8600000143051147,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1633471522","https://openalex.org/W2030822983","https://openalex.org/W2034525900","https://openalex.org/W2064139040","https://openalex.org/W2143033765","https://openalex.org/W2159448561","https://openalex.org/W2166243422","https://openalex.org/W2498970880","https://openalex.org/W2533651815","https://openalex.org/W4252370165"],"related_works":["https://openalex.org/W1981294195","https://openalex.org/W2787979264","https://openalex.org/W1566591950","https://openalex.org/W3116174323","https://openalex.org/W2284990248","https://openalex.org/W3107559600","https://openalex.org/W3173802940","https://openalex.org/W3200906996","https://openalex.org/W2071492559","https://openalex.org/W2652383716"],"abstract_inverted_index":{"This":[0],"article":[1],"presents":[2],"a":[3,25,46,88],"novel":[4],"and":[5,27],"robust":[6],"approach":[7],"for":[8,59],"implementing":[9],"ultra-low":[10],"power":[11],"MOS":[12],"current":[13,55],"mode":[14],"logic":[15],"(MCML)":[16],"circuits.":[17],"To":[18],"operate":[19],"at":[20,120],"very":[21,47],"low":[22,83,121],"bias":[23,54,80,122],"currents,":[24],"simple":[26],"compact":[28],"high":[29],"resistance":[30],"load":[31,118],"device":[32],"has":[33],"been":[34],"introduced.":[35],"Operating":[36],"in":[37,45,64],"subthreshold":[38],"regime,":[39],"the":[40,53,61,71,92,103,111],"circuit":[41,74,105],"can":[42,75],"be":[43,76],"used":[44],"wide":[48],"frequency":[49],"range":[50],"by":[51],"adjusting":[52],"without":[56],"any":[57],"need":[58],"resizing":[60],"devices.":[62],"Measurements":[63],"0.18":[65],"mum":[66],"CMOS":[67,98],"technology":[68],"show":[69,101],"that":[70,102],"proposed":[72,104],"MCML":[73,113],"operated":[77],"reliably":[78],"with":[79,115],"currents":[81],"as":[82,84],"1":[85],"nA":[86],"offering":[87],"significant":[89],"improvement":[90],"of":[91],"power-delay":[93],"product":[94],"compared":[95,109],"to":[96,110],"conventional":[97,112],"gates.":[99],"Simulations":[100],"exhibits":[106],"faster":[107],"response":[108],"circuits":[114],"triode-mode":[116],"PMOS":[117],"devices":[119],"currents.":[123]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2019,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2016,"cited_by_count":1},{"year":2012,"cited_by_count":5}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}