{"id":"https://openalex.org/W2120183389","doi":"https://doi.org/10.1109/esscirc.2007.4430259","title":"Impact of well edge proximity effect on timing","display_name":"Impact of well edge proximity effect on timing","publication_year":2007,"publication_date":"2007-09-01","ids":{"openalex":"https://openalex.org/W2120183389","doi":"https://doi.org/10.1109/esscirc.2007.4430259","mag":"2120183389"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2007.4430259","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2007.4430259","pdf_url":null,"source":{"id":"https://openalex.org/S4210191203","display_name":"Proceedings of ESSCIRC","issn_l":"1930-8833","issn":["1930-8833","2643-1319"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5067005883","display_name":"Toshiki Kanamoto","orcid":"https://orcid.org/0000-0002-6326-6960"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Toshiki Kanamoto","raw_affiliation_strings":["Renesas Technology Corp., Itami-shi, Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Renesas Technology Corp., Itami-shi, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072741891","display_name":"Yasuhiro Ogasahara","orcid":"https://orcid.org/0000-0003-2718-1756"},"institutions":[{"id":"https://openalex.org/I98285908","display_name":"The University of Osaka","ror":"https://ror.org/035t8zc32","country_code":"JP","type":"education","lineage":["https://openalex.org/I98285908"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Yasuhiro Ogasahara","raw_affiliation_strings":["Osaka University, Suita-shi, Osaka, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Osaka University, Suita-shi, Osaka, Japan","institution_ids":["https://openalex.org/I98285908"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5008643276","display_name":"Keiko Natsume","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Keiko Natsume","raw_affiliation_strings":["Renesas Technology Corp., Itami-shi, Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Renesas Technology Corp., Itami-shi, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5101846531","display_name":"Kenji Yamaguchi","orcid":"https://orcid.org/0000-0003-3313-3048"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Kenji Yamaguchi","raw_affiliation_strings":["Renesas Technology Corp., Itami-shi, Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Renesas Technology Corp., Itami-shi, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5048469827","display_name":"Hiroyuki Amishiro","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Hiroyuki Amishiro","raw_affiliation_strings":["Renesas Technology Corp., Itami-shi, Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Renesas Technology Corp., Itami-shi, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5100564175","display_name":"Tetsuya Watanabe","orcid":null},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Tetsuya Watanabe","raw_affiliation_strings":["Renesas Technology Corp., Itami-shi, Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Renesas Technology Corp., Itami-shi, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5002405139","display_name":"Masanori Hashimoto","orcid":"https://orcid.org/0000-0002-0377-2108"},"institutions":[{"id":"https://openalex.org/I4210153176","display_name":"Renesas Electronics (Japan)","ror":"https://ror.org/058wb7691","country_code":"JP","type":"company","lineage":["https://openalex.org/I4210153176"]}],"countries":["JP"],"is_corresponding":false,"raw_author_name":"Masanori Hashimoto","raw_affiliation_strings":["Renesas Technology Corp., Itami-shi, Hyogo, Japan"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Renesas Technology Corp., Itami-shi, Hyogo, Japan","institution_ids":["https://openalex.org/I4210153176"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0777,"has_fulltext":false,"cited_by_count":12,"citation_normalized_percentile":{"value":0.79922337,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"115","last_page":"118"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/nmos-logic","display_name":"NMOS logic","score":0.904145359992981},{"id":"https://openalex.org/keywords/pmos-logic","display_name":"PMOS logic","score":0.81284499168396},{"id":"https://openalex.org/keywords/enhanced-data-rates-for-gsm-evolution","display_name":"Enhanced Data Rates for GSM Evolution","score":0.6874833106994629},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.5993646383285522},{"id":"https://openalex.org/keywords/wafer","display_name":"Wafer","score":0.5531307458877563},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5249141454696655},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.5151456594467163},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.5047672986984253},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.4977743923664093},{"id":"https://openalex.org/keywords/signal-edge","display_name":"Signal edge","score":0.45738571882247925},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.38574135303497314},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.36280229687690735},{"id":"https://openalex.org/keywords/materials-science","display_name":"Materials science","score":0.3473902940750122},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.31595319509506226},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.18691113591194153},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.10900872945785522}],"concepts":[{"id":"https://openalex.org/C197162436","wikidata":"https://www.wikidata.org/wiki/Q83908","display_name":"NMOS logic","level":4,"score":0.904145359992981},{"id":"https://openalex.org/C27050352","wikidata":"https://www.wikidata.org/wiki/Q173605","display_name":"PMOS logic","level":4,"score":0.81284499168396},{"id":"https://openalex.org/C162307627","wikidata":"https://www.wikidata.org/wiki/Q204833","display_name":"Enhanced Data Rates for GSM Evolution","level":2,"score":0.6874833106994629},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.5993646383285522},{"id":"https://openalex.org/C160671074","wikidata":"https://www.wikidata.org/wiki/Q267131","display_name":"Wafer","level":2,"score":0.5531307458877563},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5249141454696655},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.5151456594467163},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.5047672986984253},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.4977743923664093},{"id":"https://openalex.org/C117525741","wikidata":"https://www.wikidata.org/wiki/Q775654","display_name":"Signal edge","level":4,"score":0.45738571882247925},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.38574135303497314},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.36280229687690735},{"id":"https://openalex.org/C192562407","wikidata":"https://www.wikidata.org/wiki/Q228736","display_name":"Materials science","level":0,"score":0.3473902940750122},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.31595319509506226},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.18691113591194153},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.10900872945785522},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.0},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2007.4430259","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2007.4430259","pdf_url":null,"source":{"id":"https://openalex.org/S4210191203","display_name":"Proceedings of ESSCIRC","issn_l":"1930-8833","issn":["1930-8833","2643-1319"],"is_oa":false,"is_in_doaj":false,"is_core":true,"host_organization":"https://openalex.org/P4310319808","host_organization_name":"Institute of Electrical and Electronics Engineers","host_organization_lineage":["https://openalex.org/P4310319808"],"host_organization_lineage_names":["Institute of Electrical and Electronics Engineers"],"type":"journal"},"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2007 - 33rd European Solid-State Circuits Conference","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"display_name":"Industry, innovation and infrastructure","id":"https://metadata.un.org/sdg/9","score":0.4699999988079071}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1990845788","https://openalex.org/W2027568818","https://openalex.org/W2042822039","https://openalex.org/W2106435698","https://openalex.org/W2116872735","https://openalex.org/W2138908082","https://openalex.org/W6661072409"],"related_works":["https://openalex.org/W4386261925","https://openalex.org/W2048420745","https://openalex.org/W2082944690","https://openalex.org/W2263373136","https://openalex.org/W1914349328","https://openalex.org/W2160067645","https://openalex.org/W2023334077","https://openalex.org/W2005494397","https://openalex.org/W2104885411","https://openalex.org/W2379197520"],"abstract_inverted_index":{"This":[0],"paper":[1],"studies":[2],"impact":[3],"of":[4,36,72],"the":[5,41,47,73,91],"well":[6,42],"edge":[7,43],"proximity":[8,44],"effect":[9,45],"on":[10,15,53],"digital":[11],"circuit":[12],"delay,":[13],"based":[14],"model":[16],"parameters":[17],"extracted":[18],"from":[19],"test":[20],"structures":[21],"in":[22,46,61,70,90],"an":[23],"industrial":[24],"65nm":[25,48,92],"wafer":[26],"process.":[27],"The":[28],"experimental":[29],"results":[30],"show":[31],"that":[32,82],"up":[33],"to":[34,58,87],"10%":[35],"delay":[37,67],"increase":[38,60],"arises":[39],"by":[40],"technology,":[49],"and":[50,63],"it":[51],"depends":[52],"interconnect":[54],"length.":[55],"Furthermore,":[56],"due":[57],"asymmetric":[59],"pMOS":[62],"nMOS":[64],"threshold":[65,74],"voltages,":[66],"may":[68],"decrease":[69],"spite":[71],"voltage":[75],"increase.":[76],"From":[77],"these":[78],"results,":[79],"we":[80],"conclude":[81],"considering":[83],"WPE":[84],"is":[85],"indispensable":[86],"cell":[88],"characterization":[89],"technology.":[93]},"counts_by_year":[{"year":2024,"cited_by_count":3},{"year":2020,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}