{"id":"https://openalex.org/W1561984905","doi":"https://doi.org/10.1109/esscirc.2003.1257157","title":"Bitline leakage equalization for sub-100nm caches","display_name":"Bitline leakage equalization for sub-100nm caches","publication_year":2004,"publication_date":"2004-07-20","ids":{"openalex":"https://openalex.org/W1561984905","doi":"https://doi.org/10.1109/esscirc.2003.1257157","mag":"1561984905"},"language":"en","primary_location":{"id":"doi:10.1109/esscirc.2003.1257157","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2003.1257157","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5029147977","display_name":"Atila Alvandpour","orcid":"https://orcid.org/0000-0001-8922-2360"},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":true,"raw_author_name":"A. Alvandpour","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5006467285","display_name":"Dinesh Somasekhar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D. Somasekhar","raw_affiliation_strings":["Circuits Research, Intel Laboratories, Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Circuits Research, Intel Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5074107306","display_name":"Ram Krishnamurthy","orcid":"https://orcid.org/0000-0002-2428-7099"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Krishnamurthy","raw_affiliation_strings":["Circuits Research, Intel Laboratories, Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Circuits Research, Intel Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5076642880","display_name":"Vivek De","orcid":"https://orcid.org/0000-0001-5207-1079"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"V. De","raw_affiliation_strings":["Circuits Research, Intel Laboratories, Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Circuits Research, Intel Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5112875487","display_name":"Shekhar Borkar","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"S. Borkar","raw_affiliation_strings":["Circuits Research, Intel Laboratories, Intel Corporation, USA"],"affiliations":[{"raw_affiliation_string":"Circuits Research, Intel Laboratories, Intel Corporation, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5112517037","display_name":"C. Svensson","orcid":null},"institutions":[{"id":"https://openalex.org/I102134673","display_name":"Link\u00f6ping University","ror":"https://ror.org/05ynxx418","country_code":"SE","type":"education","lineage":["https://openalex.org/I102134673"]}],"countries":["SE"],"is_corresponding":false,"raw_author_name":"C. Svensson","raw_affiliation_strings":["Department of Electrical Engineering, Link\u00f6ping University, Sweden"],"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, Link\u00f6ping University, Sweden","institution_ids":["https://openalex.org/I102134673"]}]}],"institutions":[],"countries_distinct_count":2,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5029147977"],"corresponding_institution_ids":["https://openalex.org/I102134673"],"apc_list":null,"apc_paid":null,"fwci":1.6458,"has_fulltext":false,"cited_by_count":22,"citation_normalized_percentile":{"value":0.82621498,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":98},"biblio":{"volume":null,"issue":null,"first_page":"401","last_page":"404"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9997000098228455,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.731529712677002},{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.6982526779174805},{"id":"https://openalex.org/keywords/sense-amplifier","display_name":"Sense amplifier","score":0.6468691825866699},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5543705821037292},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.5506375432014465},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5228500962257385},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5200528502464294},{"id":"https://openalex.org/keywords/input-offset-voltage","display_name":"Input offset voltage","score":0.5179449915885925},{"id":"https://openalex.org/keywords/offset","display_name":"Offset (computer science)","score":0.4984750747680664},{"id":"https://openalex.org/keywords/amplifier","display_name":"Amplifier","score":0.4375024139881134},{"id":"https://openalex.org/keywords/biasing","display_name":"Biasing","score":0.4226230978965759},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.4063723385334015},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.3620951175689697},{"id":"https://openalex.org/keywords/operational-amplifier","display_name":"Operational amplifier","score":0.2976101040840149},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17608016729354858}],"concepts":[{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.731529712677002},{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.6982526779174805},{"id":"https://openalex.org/C32666082","wikidata":"https://www.wikidata.org/wiki/Q7450979","display_name":"Sense amplifier","level":3,"score":0.6468691825866699},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5543705821037292},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.5506375432014465},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5228500962257385},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5200528502464294},{"id":"https://openalex.org/C63651839","wikidata":"https://www.wikidata.org/wiki/Q478566","display_name":"Input offset voltage","level":5,"score":0.5179449915885925},{"id":"https://openalex.org/C175291020","wikidata":"https://www.wikidata.org/wiki/Q1156822","display_name":"Offset (computer science)","level":2,"score":0.4984750747680664},{"id":"https://openalex.org/C194257627","wikidata":"https://www.wikidata.org/wiki/Q211554","display_name":"Amplifier","level":3,"score":0.4375024139881134},{"id":"https://openalex.org/C20254490","wikidata":"https://www.wikidata.org/wiki/Q719550","display_name":"Biasing","level":3,"score":0.4226230978965759},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.4063723385334015},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.3620951175689697},{"id":"https://openalex.org/C145366948","wikidata":"https://www.wikidata.org/wiki/Q178947","display_name":"Operational amplifier","level":4,"score":0.2976101040840149},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17608016729354858},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscirc.2003.1257157","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscirc.2003.1257157","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8100000023841858,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W2098968518","https://openalex.org/W2145536841","https://openalex.org/W2150842933","https://openalex.org/W2177426130","https://openalex.org/W2788649536"],"related_works":["https://openalex.org/W1835913819","https://openalex.org/W2548084981","https://openalex.org/W2051363901","https://openalex.org/W2127348582","https://openalex.org/W2053448087","https://openalex.org/W2136142653","https://openalex.org/W2373152541","https://openalex.org/W3085306935","https://openalex.org/W2174410816","https://openalex.org/W2146647189"],"abstract_inverted_index":{"This":[0,40],"paper":[1],"describes":[2],"a":[3,25,43,56,81,90],"leakage-tolerant":[4],"circuit":[5],"technique":[6,62],"for":[7,96,110],"embedded":[8],"sub-100nm":[9],"SRAM's.":[10],"The":[11,60],"proposed":[12,61],"8-transistor":[13],"memory":[14,86],"cells":[15,87],"inject":[16],"identical":[17],"leakage":[18,38],"currents":[19],"into":[20],"the":[21,28,32,49,65,94],"differential":[22,33,45,104],"bitlines.":[23,113],"During":[24],"read":[26,58],"operation,":[27],"active":[29],"leakage-equalization":[30],"eliminates":[31],"offset":[34],"voltage":[35,46,105],"due":[36],"to":[37,101],"currents.":[39],"results":[41],"in":[42,48],"fast":[44],"development":[47,106],"input":[50],"of":[51,76,84],"sense":[52],"amplifiers":[53],"and":[54],"therefore":[55],"faster":[57,103],"operation.":[59],"significantly":[63],"relaxes":[64],"conventional":[66],"constraint":[67],"on":[68],"device":[69],"I/sub":[70],"ON//I/sub":[71],"OFF/":[72],"ratio":[73],"versus":[74],"number":[75,83],"memory-cells":[77],"per":[78],"bitline.":[79],"Consequently,":[80],"large":[82],"leaky":[85],"can":[88],"share":[89],"single":[91],"bitline":[92,98],"eliminating":[93],"need":[95],"aggressive":[97],"partitioning.":[99],"Up":[100],"80%":[102],"has":[107],"been":[108],"observed":[109],"100nm":[111],"256-cells":[112]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":1},{"year":2023,"cited_by_count":1},{"year":2018,"cited_by_count":1},{"year":2017,"cited_by_count":2},{"year":2015,"cited_by_count":3},{"year":2014,"cited_by_count":2},{"year":2012,"cited_by_count":4}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}