{"id":"https://openalex.org/W2168885001","doi":"https://doi.org/10.1109/esscir.2005.1541678","title":"A 9-b 400 Msample/s pipelined analog-todigital converter in 90nm CMOS/sup 1/","display_name":"A 9-b 400 Msample/s pipelined analog-todigital converter in 90nm CMOS/sup 1/","publication_year":2005,"publication_date":"2005-12-10","ids":{"openalex":"https://openalex.org/W2168885001","doi":"https://doi.org/10.1109/esscir.2005.1541678","mag":"2168885001"},"language":"en","primary_location":{"id":"doi:10.1109/esscir.2005.1541678","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscir.2005.1541678","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5111918939","display_name":"C.T. Peach","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]},{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"C.T. Peach","raw_affiliation_strings":["Department of Electrical Engineering, University of Washington, Seattle, WA, USA","Intel Research and Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Washington, Seattle, WA, USA","institution_ids":["https://openalex.org/I201448701"]},{"raw_affiliation_string":"Intel Research and Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5058466731","display_name":"Ashoke Ravi","orcid":"https://orcid.org/0000-0001-8302-622X"},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Ravi","raw_affiliation_strings":["Intel Research and Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Research and Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5012867674","display_name":"R. Bishop","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"R. Bishop","raw_affiliation_strings":["Intel Research and Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Research and Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5062357544","display_name":"K. Soumyanath","orcid":null},"institutions":[{"id":"https://openalex.org/I1343180700","display_name":"Intel (United States)","ror":"https://ror.org/01ek73717","country_code":"US","type":"company","lineage":["https://openalex.org/I1343180700"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"K. Soumyanath","raw_affiliation_strings":["Intel Research and Development, Intel Corporation, Hillsboro, OR, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Intel Research and Development, Intel Corporation, Hillsboro, OR, USA","institution_ids":["https://openalex.org/I1343180700"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5033673209","display_name":"D.J. Allstot","orcid":"https://orcid.org/0000-0002-2296-7728"},"institutions":[{"id":"https://openalex.org/I201448701","display_name":"University of Washington","ror":"https://ror.org/00cvxb145","country_code":"US","type":"education","lineage":["https://openalex.org/I201448701"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"D.J. Allstot","raw_affiliation_strings":["Department of Electrical Engineering, University of Washington, Seattle, WA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering, University of Washington, Seattle, WA, USA","institution_ids":["https://openalex.org/I201448701"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2992,"has_fulltext":false,"cited_by_count":5,"citation_normalized_percentile":{"value":0.66062771,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"535","last_page":"538"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10187","display_name":"Radio Frequency Integrated Circuit Design","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":0.9988999962806702,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/oversampling","display_name":"Oversampling","score":0.6944131851196289},{"id":"https://openalex.org/keywords/pipeline","display_name":"Pipeline (software)","score":0.594685971736908},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5812497138977051},{"id":"https://openalex.org/keywords/skew","display_name":"Skew","score":0.557166576385498},{"id":"https://openalex.org/keywords/effective-number-of-bits","display_name":"Effective number of bits","score":0.553096354007721},{"id":"https://openalex.org/keywords/capacitor","display_name":"Capacitor","score":0.5469125509262085},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.543179452419281},{"id":"https://openalex.org/keywords/successive-approximation-adc","display_name":"Successive approximation ADC","score":0.5141239762306213},{"id":"https://openalex.org/keywords/sampling","display_name":"Sampling (signal processing)","score":0.4830232560634613},{"id":"https://openalex.org/keywords/sample-and-hold","display_name":"Sample and hold","score":0.467207133769989},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.45591768622398376},{"id":"https://openalex.org/keywords/switched-capacitor","display_name":"Switched capacitor","score":0.4405364990234375},{"id":"https://openalex.org/keywords/bandwidth","display_name":"Bandwidth (computing)","score":0.42680612206459045},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3039248585700989},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.2920220196247101},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.251943975687027},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.1917072832584381},{"id":"https://openalex.org/keywords/telecommunications","display_name":"Telecommunications","score":0.09446820616722107}],"concepts":[{"id":"https://openalex.org/C197323446","wikidata":"https://www.wikidata.org/wiki/Q331222","display_name":"Oversampling","level":3,"score":0.6944131851196289},{"id":"https://openalex.org/C43521106","wikidata":"https://www.wikidata.org/wiki/Q2165493","display_name":"Pipeline (software)","level":2,"score":0.594685971736908},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5812497138977051},{"id":"https://openalex.org/C43711488","wikidata":"https://www.wikidata.org/wiki/Q7534783","display_name":"Skew","level":2,"score":0.557166576385498},{"id":"https://openalex.org/C16671190","wikidata":"https://www.wikidata.org/wiki/Q505579","display_name":"Effective number of bits","level":3,"score":0.553096354007721},{"id":"https://openalex.org/C52192207","wikidata":"https://www.wikidata.org/wiki/Q5322","display_name":"Capacitor","level":3,"score":0.5469125509262085},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.543179452419281},{"id":"https://openalex.org/C60154766","wikidata":"https://www.wikidata.org/wiki/Q2650458","display_name":"Successive approximation ADC","level":4,"score":0.5141239762306213},{"id":"https://openalex.org/C140779682","wikidata":"https://www.wikidata.org/wiki/Q210868","display_name":"Sampling (signal processing)","level":3,"score":0.4830232560634613},{"id":"https://openalex.org/C206565188","wikidata":"https://www.wikidata.org/wiki/Q836482","display_name":"Sample and hold","level":3,"score":0.467207133769989},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.45591768622398376},{"id":"https://openalex.org/C103357873","wikidata":"https://www.wikidata.org/wiki/Q572656","display_name":"Switched capacitor","level":4,"score":0.4405364990234375},{"id":"https://openalex.org/C2776257435","wikidata":"https://www.wikidata.org/wiki/Q1576430","display_name":"Bandwidth (computing)","level":2,"score":0.42680612206459045},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3039248585700989},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.2920220196247101},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.251943975687027},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.1917072832584381},{"id":"https://openalex.org/C76155785","wikidata":"https://www.wikidata.org/wiki/Q418","display_name":"Telecommunications","level":1,"score":0.09446820616722107},{"id":"https://openalex.org/C94915269","wikidata":"https://www.wikidata.org/wiki/Q1834857","display_name":"Detector","level":2,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscir.2005.1541678","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscir.2005.1541678","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8899999856948853,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1553282838","https://openalex.org/W1564201208","https://openalex.org/W1750390948","https://openalex.org/W1984886993","https://openalex.org/W2033845134","https://openalex.org/W2114228040","https://openalex.org/W2123816021","https://openalex.org/W2140351762","https://openalex.org/W2158827048"],"related_works":["https://openalex.org/W2914701507","https://openalex.org/W2905521207","https://openalex.org/W2168717468","https://openalex.org/W2161345192","https://openalex.org/W2059269782","https://openalex.org/W2783221760","https://openalex.org/W3156142317","https://openalex.org/W4292071990","https://openalex.org/W3216962587","https://openalex.org/W4386861788"],"abstract_inverted_index":{"A":[0,85],"9-bit":[1],"400MS/s":[2],"pipelined":[3],"analog-to-digital":[4],"converter":[5,16],"(ADC)":[6],"targeted":[7],"for":[8,59,81],"emerging":[9],"wireless":[10],"LAN":[11],"applications":[12],"is":[13,67],"presented.":[14],"The":[15,39,65],"can":[17],"be":[18],"clocked":[19],"up":[20],"to":[21],"500":[22],"mega-samples":[23],"per":[24],"second":[25],"(MSPS)":[26],"with":[27],"an":[28],"input":[29,50],"bandwidth":[30],"of":[31,45,77],"100":[32],"MHz,":[33],"while":[34],"drawing":[35],"93mA":[36],"from":[37],"1.5V.":[38],"ADC":[40],"achieves":[41],"8.6":[42],"effective":[43],"number":[44],"bits":[46],"(ENOBs)":[47],"at":[48,54],"10MHz":[49],"and":[51],"7.9":[52],"ENOBs":[53],"80MHz":[55],"input,":[56],"without":[57],"accounting":[58],"calibration":[60],"or":[61],"oversampling":[62],"based":[63],"enhancements.":[64],"architecture":[66],"a":[68],"double-sampled":[69],"switched-capacitor":[70],"pipeline":[71],"that":[72],"converts":[73],"on":[74],"both":[75],"phases":[76],"the":[78],"sampling":[79,95],"clock":[80],"improved":[82],"power":[83],"efficiency.":[84],"skew-insensitive":[86],"sample-and-hold":[87],"stage":[88],"attenuates":[89],"distortion":[90],"caused":[91],"by":[92],"imperfectly":[93],"phased":[94],"clocks.":[96]},"counts_by_year":[{"year":2016,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}