{"id":"https://openalex.org/W1600994270","doi":"https://doi.org/10.1109/esscir.2005.1541662","title":"A built-in I/sub DDQ/ testing circuit","display_name":"A built-in I/sub DDQ/ testing circuit","publication_year":2005,"publication_date":"2005-12-10","ids":{"openalex":"https://openalex.org/W1600994270","doi":"https://doi.org/10.1109/esscir.2005.1541662","mag":"1600994270"},"language":"en","primary_location":{"id":"doi:10.1109/esscir.2005.1541662","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscir.2005.1541662","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","raw_type":"proceedings-article"},"type":"preprint","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109172816","display_name":"S. Matakias","orcid":null},"institutions":[{"id":"https://openalex.org/I73142707","display_name":"Athens University of Economics and Business","ror":"https://ror.org/03s262162","country_code":"GR","type":"education","lineage":["https://openalex.org/I73142707"]},{"id":"https://openalex.org/I200777214","display_name":"National and Kapodistrian University of Athens","ror":"https://ror.org/04gnjpq42","country_code":"GR","type":"education","lineage":["https://openalex.org/I200777214"]}],"countries":["GR"],"is_corresponding":true,"raw_author_name":"S. Matakias","raw_affiliation_strings":["Department of Informatics & Telecommunications, University of Athens (NKUA), Athens, Greece","CS-AUEB - Department of Informatics [Athens] (\u03a0\u03b1\u03c4\u03b7\u03c3\u03af\u03c9\u03bd 76, \u0391\u03b8\u03ae\u03bd\u03b1 104 34, \u03a4\u03b7\u03bb. \u0393\u03c1\u03b1\u03bc\u03bc\u03b1\u03c4\u03b5\u03af\u03b1\u03c2 76, Patission Str. / GR10434 Athens - Greece)"],"affiliations":[{"raw_affiliation_string":"Department of Informatics & Telecommunications, University of Athens (NKUA), Athens, Greece","institution_ids":["https://openalex.org/I200777214"]},{"raw_affiliation_string":"CS-AUEB - Department of Informatics [Athens] (\u03a0\u03b1\u03c4\u03b7\u03c3\u03af\u03c9\u03bd 76, \u0391\u03b8\u03ae\u03bd\u03b1 104 34, \u03a4\u03b7\u03bb. \u0393\u03c1\u03b1\u03bc\u03bc\u03b1\u03c4\u03b5\u03af\u03b1\u03c2 76, Patission Str. / GR10434 Athens - Greece)","institution_ids":["https://openalex.org/I73142707"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5036684985","display_name":"Yiorgos Tsiatouhas","orcid":"https://orcid.org/0000-0001-8408-6929"},"institutions":[{"id":"https://openalex.org/I194019607","display_name":"University of Ioannina","ror":"https://ror.org/01qg3j183","country_code":"GR","type":"education","lineage":["https://openalex.org/I194019607"]},{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"Y. Tsiatouhas","raw_affiliation_strings":["Department Computer Science, University of Ioannina (UoI), Ioannina, Greece","Department of Computer Engineering and Informatics [Patras] (Rio, 26500 Patras - Greece)"],"affiliations":[{"raw_affiliation_string":"Department Computer Science, University of Ioannina (UoI), Ioannina, Greece","institution_ids":["https://openalex.org/I194019607"]},{"raw_affiliation_string":"Department of Computer Engineering and Informatics [Patras] (Rio, 26500 Patras - Greece)","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5114019291","display_name":"A. Arapoyanni","orcid":null},"institutions":[{"id":"https://openalex.org/I73142707","display_name":"Athens University of Economics and Business","ror":"https://ror.org/03s262162","country_code":"GR","type":"education","lineage":["https://openalex.org/I73142707"]},{"id":"https://openalex.org/I200777214","display_name":"National and Kapodistrian University of Athens","ror":"https://ror.org/04gnjpq42","country_code":"GR","type":"education","lineage":["https://openalex.org/I200777214"]}],"countries":["GR"],"is_corresponding":false,"raw_author_name":"A. Arapoyanni","raw_affiliation_strings":["Department of Informatics & Telecommunications, University of Athens (NKUA), Athens, Greece","CS-AUEB - Department of Informatics [Athens] (\u03a0\u03b1\u03c4\u03b7\u03c3\u03af\u03c9\u03bd 76, \u0391\u03b8\u03ae\u03bd\u03b1 104 34, \u03a4\u03b7\u03bb. \u0393\u03c1\u03b1\u03bc\u03bc\u03b1\u03c4\u03b5\u03af\u03b1\u03c2 76, Patission Str. / GR10434 Athens - Greece)"],"affiliations":[{"raw_affiliation_string":"Department of Informatics & Telecommunications, University of Athens (NKUA), Athens, Greece","institution_ids":["https://openalex.org/I200777214"]},{"raw_affiliation_string":"CS-AUEB - Department of Informatics [Athens] (\u03a0\u03b1\u03c4\u03b7\u03c3\u03af\u03c9\u03bd 76, \u0391\u03b8\u03ae\u03bd\u03b1 104 34, \u03a4\u03b7\u03bb. \u0393\u03c1\u03b1\u03bc\u03bc\u03b1\u03c4\u03b5\u03af\u03b1\u03c2 76, Patission Str. / GR10434 Athens - Greece)","institution_ids":["https://openalex.org/I73142707"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108504905","display_name":"Th. Haniotakis","orcid":null},"institutions":[{"id":"https://openalex.org/I110378019","display_name":"Southern Illinois University Carbondale","ror":"https://ror.org/049kefs16","country_code":"US","type":"education","lineage":["https://openalex.org/I110378019","https://openalex.org/I2801502357"]},{"id":"https://openalex.org/I174878644","display_name":"University of Patras","ror":"https://ror.org/017wvtq80","country_code":"GR","type":"education","lineage":["https://openalex.org/I174878644"]}],"countries":["GR","US"],"is_corresponding":false,"raw_author_name":"Th. Haniotakis","raw_affiliation_strings":["Department of Electrical & Computer Engineering, Southem Illinois University, Carbondale, IL, USA","Department of Computer Engineering and Informatics [Patras] (Rio, 26500 Patras - Greece)"],"affiliations":[{"raw_affiliation_string":"Department of Electrical & Computer Engineering, Southem Illinois University, Carbondale, IL, USA","institution_ids":["https://openalex.org/I110378019"]},{"raw_affiliation_string":"Department of Computer Engineering and Informatics [Patras] (Rio, 26500 Patras - Greece)","institution_ids":["https://openalex.org/I174878644"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5108138014","display_name":"G. Prenat","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"G. Prenat","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5107869413","display_name":"S. Mir","orcid":null},"institutions":[{"id":"https://openalex.org/I4210087012","display_name":"Techniques of Informatics and Microelectronics for Integrated Systems Architecture","ror":"https://ror.org/000063q30","country_code":"FR","type":"facility","lineage":["https://openalex.org/I106785703","https://openalex.org/I1294671590","https://openalex.org/I1294671590","https://openalex.org/I4210087012","https://openalex.org/I4210159245","https://openalex.org/I899635006","https://openalex.org/I899635006"]}],"countries":["FR"],"is_corresponding":false,"raw_author_name":"S. Mir","raw_affiliation_strings":["TIMA Laboratory, Grenoble, France","TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)"],"affiliations":[{"raw_affiliation_string":"TIMA Laboratory, Grenoble, France","institution_ids":["https://openalex.org/I4210087012"]},{"raw_affiliation_string":"TIMA - Techniques de l'Informatique et de la Micro\u00e9lectronique pour l'Architecture des syst\u00e8mes int\u00e9gr\u00e9s (46 avenue F\u00e9lix Viallet\r\n38031 GRENOBLE Cedex 1 - France)","institution_ids":["https://openalex.org/I4210087012"]}]}],"institutions":[],"countries_distinct_count":3,"institutions_distinct_count":6,"corresponding_author_ids":["https://openalex.org/A5109172816"],"corresponding_institution_ids":["https://openalex.org/I200777214","https://openalex.org/I73142707"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.06812987,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"471","last_page":"474"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.7176252603530884},{"id":"https://openalex.org/keywords/iddq-testing","display_name":"Iddq testing","score":0.6646166443824768},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.5917156338691711},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5723304152488708},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.46911221742630005},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.45001617074012756},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.3807384967803955},{"id":"https://openalex.org/keywords/reliability-engineering","display_name":"Reliability engineering","score":0.33366137742996216},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.30258482694625854},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.10875779390335083}],"concepts":[{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.7176252603530884},{"id":"https://openalex.org/C206678392","wikidata":"https://www.wikidata.org/wiki/Q5987815","display_name":"Iddq testing","level":3,"score":0.6646166443824768},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.5917156338691711},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5723304152488708},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.46911221742630005},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.45001617074012756},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.3807384967803955},{"id":"https://openalex.org/C200601418","wikidata":"https://www.wikidata.org/wiki/Q2193887","display_name":"Reliability engineering","level":1,"score":0.33366137742996216},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.30258482694625854},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.10875779390335083},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0}],"mesh":[],"locations_count":2,"locations":[{"id":"doi:10.1109/esscir.2005.1541662","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscir.2005.1541662","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:HAL:hal-00079771v1","is_oa":false,"landing_page_url":"https://hal.science/hal-00079771","pdf_url":null,"source":{"id":"https://openalex.org/S4406922461","display_name":"SPIRE - Sciences Po Institutional REpository","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":null,"host_organization_name":null,"host_organization_lineage":[],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"Solid-State Circuits Conference, 2005. ESSCIRC 2005. Proceedings of the 31st European, 2005, Grenoble, France. pp.471- 474, ⟨10.1109/ESSCIR.2005.1541662⟩","raw_type":"Conference papers"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1993974694","https://openalex.org/W2083626899","https://openalex.org/W2120750915","https://openalex.org/W2125263803","https://openalex.org/W2132851135","https://openalex.org/W2142434170","https://openalex.org/W2145190831","https://openalex.org/W2541847111","https://openalex.org/W4246588278","https://openalex.org/W4253620068"],"related_works":["https://openalex.org/W2164017138","https://openalex.org/W2181536841","https://openalex.org/W2946329844","https://openalex.org/W2121399123","https://openalex.org/W1549631873","https://openalex.org/W2151105402","https://openalex.org/W2075762290","https://openalex.org/W2102383741","https://openalex.org/W2111156521","https://openalex.org/W2114987195"],"abstract_inverted_index":{"Although":[0],"I/sub":[1,35,48],"DDQ/":[2,36,49],"testing":[3,37,50],"has":[4],"become":[5],"a":[6,33],"widely":[7],"accepted":[8],"defect":[9],"detection":[10],"technique":[11],"for":[12],"CMOS":[13],"ICs,":[14],"its":[15],"effectiveness":[16],"in":[17,51],"very":[18],"deep":[19],"submicron":[20],"technologies":[21,53],"is":[22,39],"threatened":[23],"by":[24],"the":[25,45],"increased":[26],"transistor":[27],"leakage":[28],"current.":[29],"In":[30],"this":[31],"paper,":[32],"built-in":[34],"circuit":[38],"presented,":[40],"that":[41],"aims":[42],"to":[43],"extend":[44],"viability":[46],"of":[47],"future":[52],"and":[54],"first":[55],"experimental":[56],"results":[57],"are":[58],"discussed.":[59]},"counts_by_year":[{"year":2015,"cited_by_count":1}],"updated_date":"2026-03-28T08:17:26.163206","created_date":"2016-06-24T00:00:00"}