{"id":"https://openalex.org/W2151614652","doi":"https://doi.org/10.1109/esscir.2005.1541635","title":"Analyzing static noise margin for subthreshold SRAM in 65nm CMOS","display_name":"Analyzing static noise margin for subthreshold SRAM in 65nm CMOS","publication_year":2005,"publication_date":"2005-12-10","ids":{"openalex":"https://openalex.org/W2151614652","doi":"https://doi.org/10.1109/esscir.2005.1541635","mag":"2151614652"},"language":"en","primary_location":{"id":"doi:10.1109/esscir.2005.1541635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscir.2005.1541635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","raw_type":"proceedings-article"},"type":"conference-paper","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5080557997","display_name":"Benton H. Calhoun","orcid":"https://orcid.org/0000-0002-3770-5050"},"institutions":[{"id":"https://openalex.org/I4210110987","display_name":"IIT@MIT","ror":"https://ror.org/01wp8zh54","country_code":"US","type":"facility","lineage":["https://openalex.org/I30771326","https://openalex.org/I4210110987"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"B.H. Calhoun","raw_affiliation_strings":["MIT, Cambridge, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MIT, Cambridge, MA, USA","institution_ids":["https://openalex.org/I4210110987"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5084128470","display_name":"Anantha P. Chandrakasan","orcid":"https://orcid.org/0000-0002-5977-2748"},"institutions":[{"id":"https://openalex.org/I4210110987","display_name":"IIT@MIT","ror":"https://ror.org/01wp8zh54","country_code":"US","type":"facility","lineage":["https://openalex.org/I30771326","https://openalex.org/I4210110987"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"A. Chandrakasan","raw_affiliation_strings":["MIT, Cambridge, MA, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"MIT, Cambridge, MA, USA","institution_ids":["https://openalex.org/I4210110987"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":1,"corresponding_author_ids":[],"corresponding_institution_ids":["https://openalex.org/I4210110987"],"apc_list":null,"apc_paid":null,"fwci":null,"has_fulltext":false,"cited_by_count":111,"citation_normalized_percentile":null,"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"363","last_page":"366"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/static-random-access-memory","display_name":"Static random-access memory","score":0.903378963470459},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.7377711534500122},{"id":"https://openalex.org/keywords/process-variation","display_name":"Process variation","score":0.7349604368209839},{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.728793740272522},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5959916114807129},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5603489875793457},{"id":"https://openalex.org/keywords/margin","display_name":"Margin (machine learning)","score":0.5551877021789551},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.5148243308067322},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5089151859283447},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.4505022168159485},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.449128121137619},{"id":"https://openalex.org/keywords/process-corners","display_name":"Process corners","score":0.4470067024230957},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4200061559677124},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.4181605875492096},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.31151849031448364},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2405821979045868}],"concepts":[{"id":"https://openalex.org/C68043766","wikidata":"https://www.wikidata.org/wiki/Q267416","display_name":"Static random-access memory","level":2,"score":0.903378963470459},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.7377711534500122},{"id":"https://openalex.org/C93389723","wikidata":"https://www.wikidata.org/wiki/Q7247313","display_name":"Process variation","level":3,"score":0.7349604368209839},{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.728793740272522},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5959916114807129},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5603489875793457},{"id":"https://openalex.org/C774472","wikidata":"https://www.wikidata.org/wiki/Q6760393","display_name":"Margin (machine learning)","level":2,"score":0.5551877021789551},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.5148243308067322},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5089151859283447},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.4505022168159485},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.449128121137619},{"id":"https://openalex.org/C192615534","wikidata":"https://www.wikidata.org/wiki/Q7247268","display_name":"Process corners","level":3,"score":0.4470067024230957},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4200061559677124},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.4181605875492096},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.31151849031448364},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2405821979045868},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.0},{"id":"https://openalex.org/C119857082","wikidata":"https://www.wikidata.org/wiki/Q2539","display_name":"Machine learning","level":1,"score":0.0},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/esscir.2005.1541635","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscir.2005.1541635","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy","score":0.5400000214576721}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":12,"referenced_works":["https://openalex.org/W160671272","https://openalex.org/W1491082069","https://openalex.org/W1589130434","https://openalex.org/W1963836677","https://openalex.org/W2002612140","https://openalex.org/W2010388475","https://openalex.org/W2100503779","https://openalex.org/W2168101540","https://openalex.org/W2170331381","https://openalex.org/W4237030520","https://openalex.org/W4248880206","https://openalex.org/W6629261333"],"related_works":["https://openalex.org/W2117824263","https://openalex.org/W2134421493","https://openalex.org/W2119312496","https://openalex.org/W4247460323","https://openalex.org/W3086682201","https://openalex.org/W2743772479","https://openalex.org/W2107909712","https://openalex.org/W2118528827","https://openalex.org/W2615230521","https://openalex.org/W2537086382"],"abstract_inverted_index":{"This":[0],"paper":[1],"evaluates":[2],"the":[3,17,52,65,68],"static":[4],"noise":[5],"margin":[6],"(SNM)":[7],"of":[8,19,55,67],"6T":[9],"SRAM":[10],"bitcells":[11],"operating":[12],"in":[13,45],"sub-threshold.":[14],"We":[15,50],"analyze":[16,51],"dependence":[18],"SNM":[20,56,72],"during":[21],"both":[22],"hold":[23],"and":[24,41,60],"read":[25],"modes":[26],"on":[27],"supply":[28],"voltage,":[29],"temperature,":[30],"transistor":[31,34],"sizes,":[32],"local":[33],"mismatch":[35],"due":[36],"to":[37],"random":[38],"doping":[39],"variation,":[40],"global":[42],"process":[43,58],"variation":[44,59],"a":[46,62],"commercial":[47],"65nm":[48],"technology.":[49],"statistical":[53],"distribution":[54],"with":[57],"provide":[61],"model":[63],"for":[64],"tail":[66],"PDF":[69],"that":[70],"dominates":[71],"failures.":[73]},"counts_by_year":[{"year":2026,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2020,"cited_by_count":2},{"year":2019,"cited_by_count":4},{"year":2018,"cited_by_count":8},{"year":2017,"cited_by_count":8},{"year":2016,"cited_by_count":14},{"year":2015,"cited_by_count":7},{"year":2014,"cited_by_count":9},{"year":2013,"cited_by_count":8},{"year":2012,"cited_by_count":3}],"updated_date":"2026-07-14T23:27:15.235271","created_date":"2025-10-10T00:00:00"}