{"id":"https://openalex.org/W1585913023","doi":"https://doi.org/10.1109/esscir.2005.1541582","title":"Low leakage design of LUT-based FPGAs","display_name":"Low leakage design of LUT-based FPGAs","publication_year":2005,"publication_date":"2005-12-10","ids":{"openalex":"https://openalex.org/W1585913023","doi":"https://doi.org/10.1109/esscir.2005.1541582","mag":"1585913023"},"language":"en","primary_location":{"id":"doi:10.1109/esscir.2005.1541582","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscir.2005.1541582","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5083656325","display_name":"Andrea Lodi","orcid":"https://orcid.org/0000-0001-9269-633X"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"A. Lodi","raw_affiliation_strings":["ARCES, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARCES, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5089473560","display_name":"Luca Ciccarelli","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"L. Ciccarelli","raw_affiliation_strings":["ARCES, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARCES, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5072885915","display_name":"Domenico Loparco","orcid":null},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"D. Loparco","raw_affiliation_strings":["ARCES, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARCES, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5044201884","display_name":"R. Canegallo","orcid":"https://orcid.org/0000-0002-3381-0697"},"institutions":[{"id":"https://openalex.org/I4210154781","display_name":"STMicroelectronics (Italy)","ror":"https://ror.org/053bqv655","country_code":"IT","type":"company","lineage":["https://openalex.org/I131827901","https://openalex.org/I4210154781"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Canegallo","raw_affiliation_strings":["STMicroelectronics, Agrate-Brianza, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"STMicroelectronics, Agrate-Brianza, Italy","institution_ids":["https://openalex.org/I4210154781"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5040667886","display_name":"R. Guerrieri","orcid":"https://orcid.org/0000-0002-8601-6884"},"institutions":[{"id":"https://openalex.org/I9360294","display_name":"University of Bologna","ror":"https://ror.org/01111rn36","country_code":"IT","type":"education","lineage":["https://openalex.org/I9360294"]}],"countries":["IT"],"is_corresponding":false,"raw_author_name":"R. Guerrieri","raw_affiliation_strings":["ARCES, University of Bologna, Bologna, Italy"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"ARCES, University of Bologna, Bologna, Italy","institution_ids":["https://openalex.org/I9360294"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":5,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0903,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.7772229,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"153","last_page":"156"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9995999932289124,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/subthreshold-conduction","display_name":"Subthreshold conduction","score":0.7251129150390625},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.7176807522773743},{"id":"https://openalex.org/keywords/lookup-table","display_name":"Lookup table","score":0.6901213526725769},{"id":"https://openalex.org/keywords/leakage","display_name":"Leakage (economics)","score":0.6894434690475464},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6041973233222961},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5939821600914001},{"id":"https://openalex.org/keywords/power-consumption","display_name":"Power consumption","score":0.5686810612678528},{"id":"https://openalex.org/keywords/leakage-power","display_name":"Leakage power","score":0.5278429985046387},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.4885481297969818},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.4470321536064148},{"id":"https://openalex.org/keywords/low-power-electronics","display_name":"Low-power electronics","score":0.44593456387519836},{"id":"https://openalex.org/keywords/very-large-scale-integration","display_name":"Very-large-scale integration","score":0.4362589418888092},{"id":"https://openalex.org/keywords/node","display_name":"Node (physics)","score":0.4191229045391083},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3696916699409485},{"id":"https://openalex.org/keywords/power","display_name":"Power (physics)","score":0.33971166610717773},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.30772829055786133},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.17933622002601624}],"concepts":[{"id":"https://openalex.org/C156465305","wikidata":"https://www.wikidata.org/wiki/Q1658601","display_name":"Subthreshold conduction","level":4,"score":0.7251129150390625},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.7176807522773743},{"id":"https://openalex.org/C134835016","wikidata":"https://www.wikidata.org/wiki/Q690265","display_name":"Lookup table","level":2,"score":0.6901213526725769},{"id":"https://openalex.org/C2777042071","wikidata":"https://www.wikidata.org/wiki/Q6509304","display_name":"Leakage (economics)","level":2,"score":0.6894434690475464},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6041973233222961},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5939821600914001},{"id":"https://openalex.org/C2984118289","wikidata":"https://www.wikidata.org/wiki/Q29954","display_name":"Power consumption","level":3,"score":0.5686810612678528},{"id":"https://openalex.org/C2987719587","wikidata":"https://www.wikidata.org/wiki/Q1811428","display_name":"Leakage power","level":4,"score":0.5278429985046387},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.4885481297969818},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.4470321536064148},{"id":"https://openalex.org/C117551214","wikidata":"https://www.wikidata.org/wiki/Q6692774","display_name":"Low-power electronics","level":4,"score":0.44593456387519836},{"id":"https://openalex.org/C14580979","wikidata":"https://www.wikidata.org/wiki/Q876049","display_name":"Very-large-scale integration","level":2,"score":0.4362589418888092},{"id":"https://openalex.org/C62611344","wikidata":"https://www.wikidata.org/wiki/Q1062658","display_name":"Node (physics)","level":2,"score":0.4191229045391083},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3696916699409485},{"id":"https://openalex.org/C163258240","wikidata":"https://www.wikidata.org/wiki/Q25342","display_name":"Power (physics)","level":2,"score":0.33971166610717773},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.30772829055786133},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.17933622002601624},{"id":"https://openalex.org/C62520636","wikidata":"https://www.wikidata.org/wiki/Q944","display_name":"Quantum mechanics","level":1,"score":0.0},{"id":"https://openalex.org/C66938386","wikidata":"https://www.wikidata.org/wiki/Q633538","display_name":"Structural engineering","level":1,"score":0.0},{"id":"https://openalex.org/C139719470","wikidata":"https://www.wikidata.org/wiki/Q39680","display_name":"Macroeconomics","level":1,"score":0.0},{"id":"https://openalex.org/C199360897","wikidata":"https://www.wikidata.org/wiki/Q9143","display_name":"Programming language","level":1,"score":0.0},{"id":"https://openalex.org/C162324750","wikidata":"https://www.wikidata.org/wiki/Q8134","display_name":"Economics","level":0,"score":0.0},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.0}],"mesh":[],"locations_count":3,"locations":[{"id":"doi:10.1109/esscir.2005.1541582","is_oa":false,"landing_page_url":"https://doi.org/10.1109/esscir.2005.1541582","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005.","raw_type":"proceedings-article"},{"id":"pmh:oai:cris.unibo.it:11585/8107","is_oa":false,"landing_page_url":"http://hdl.handle.net/11585/8107","pdf_url":null,"source":{"id":"https://openalex.org/S4306402579","display_name":"Archivio istituzionale della ricerca (Alma Mater Studiorum Universit\u00e0 di Bologna)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I4210117483","host_organization_name":"Istituto di Ematologia di Bologna","host_organization_lineage":["https://openalex.org/I4210117483"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"info:eu-repo/semantics/conferenceObject"},{"id":"pmh:oai:publications.polymtl.ca:23916","is_oa":false,"landing_page_url":"https://publications.polymtl.ca/23916/","pdf_url":null,"source":{"id":"https://openalex.org/S4306401013","display_name":"PolyPublie (\u00c9cole Polytechnique de Montr\u00e9al)","issn_l":null,"issn":null,"is_oa":false,"is_in_doaj":false,"is_core":false,"host_organization":"https://openalex.org/I45683168","host_organization_name":"Polytechnique Montr\u00e9al","host_organization_lineage":["https://openalex.org/I45683168"],"host_organization_lineage_names":[],"type":"repository"},"license":null,"license_id":null,"version":"submittedVersion","is_accepted":false,"is_published":false,"raw_source_name":"","raw_type":"Communication de conf\u00e9rence"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/7","score":0.8799999952316284,"display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":11,"referenced_works":["https://openalex.org/W1557877906","https://openalex.org/W2035004026","https://openalex.org/W2039097694","https://openalex.org/W2126357937","https://openalex.org/W2126700722","https://openalex.org/W2128602802","https://openalex.org/W2151731855","https://openalex.org/W2298000651","https://openalex.org/W4242532423","https://openalex.org/W6633444049","https://openalex.org/W6678876518"],"related_works":["https://openalex.org/W2020064877","https://openalex.org/W2155436096","https://openalex.org/W2802274608","https://openalex.org/W2107093723","https://openalex.org/W2056387586","https://openalex.org/W2167755006","https://openalex.org/W1515931217","https://openalex.org/W2545960595","https://openalex.org/W1608393288","https://openalex.org/W2122945703"],"abstract_inverted_index":{"Moving":[0],"to":[1,21,43,73],"the":[2,31,39,47,98,104],"90nm":[3],"node":[4],"and":[5,26,63,78,89,113],"below,":[6],"in":[7,57],"FPGA":[8],"architectures,":[9],"where":[10],"there's":[11],"a":[12,55,70,114],"large":[13],"number":[14],"of":[15,51,59],"inactive":[16,62,99],"transistors,":[17],"power":[18,66,101],"consumption":[19],"due":[20],"subthreshold":[22],"current":[23,41],"becomes":[24],"more":[25,27],"relevant":[28],"compared":[29],"with":[30],"switching":[32],"one.":[33],"In":[34],"this":[35],"paper":[36],"we":[37,96],"analyze":[38],"leakage":[40,65,100],"associated":[42],"look":[44],"up":[45],"tables,":[46],"basic":[48],"elaboration":[49],"units":[50],"LUT-based":[52],"FPGAs,":[53],"giving":[54],"characterization":[56],"terms":[58],"timing":[60],"performance,":[61],"active":[64,105],"consumption.":[67],"We":[68],"propose":[69],"circuit":[71],"implementation":[72],"reduce":[74,97],"leakage,":[75],"avoiding":[76],"delay":[77,111],"silicon":[79,116],"area":[80,117],"increase.":[81,118],"The":[82],"adopted":[83],"solutions":[84],"are":[85],"based":[86],"on":[87],"multi-threshold":[88],"self":[90],"reverse":[91],"biasing":[92],"techniques.":[93],"As":[94],"results":[95],"by":[102,107],"88%,":[103],"one":[106],"64%,":[108],"having":[109],"5%":[110],"degradation":[112],"negligible":[115]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2014,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
