{"id":"https://openalex.org/W7117994873","doi":"https://doi.org/10.1109/enc68268.2025.11311720","title":"Simulation of Flash Memory Architecture Using VHDL in Xilinx ISE","display_name":"Simulation of Flash Memory Architecture Using VHDL in Xilinx ISE","publication_year":2025,"publication_date":"2025-11-10","ids":{"openalex":"https://openalex.org/W7117994873","doi":"https://doi.org/10.1109/enc68268.2025.11311720"},"language":null,"primary_location":{"id":"doi:10.1109/enc68268.2025.11311720","is_oa":false,"landing_page_url":"https://doi.org/10.1109/enc68268.2025.11311720","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Mexican International Conference on Computer Science (ENC)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5121788752","display_name":"Ram\u00edrez-Cruz U. D.","orcid":null},"institutions":[{"id":"https://openalex.org/I147280213","display_name":"Universidad Veracruzana","ror":"https://ror.org/03efxn362","country_code":"MX","type":"education","lineage":["https://openalex.org/I147280213"]}],"countries":["MX"],"is_corresponding":true,"raw_author_name":"Ram\u00edrez-Cruz U. D.","raw_affiliation_strings":["Micro and Nanotechnology Research Center, Universidad Veracruzana,Veracruz,M&#x00E9;xico"],"affiliations":[{"raw_affiliation_string":"Micro and Nanotechnology Research Center, Universidad Veracruzana,Veracruz,M&#x00E9;xico","institution_ids":["https://openalex.org/I147280213"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5121804313","display_name":"Zapata-Rodr\u00edguez U.G.","orcid":null},"institutions":[{"id":"https://openalex.org/I147280213","display_name":"Universidad Veracruzana","ror":"https://ror.org/03efxn362","country_code":"MX","type":"education","lineage":["https://openalex.org/I147280213"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Zapata-Rodr\u00edguez U.G.","raw_affiliation_strings":["Universidad Veracruzana,Faculty of Mechanical and Naval Sciences Engineering,M&#x00E9;xico,Veracruz"],"affiliations":[{"raw_affiliation_string":"Universidad Veracruzana,Faculty of Mechanical and Naval Sciences Engineering,M&#x00E9;xico,Veracruz","institution_ids":["https://openalex.org/I147280213"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5121804313","display_name":"Zapata-Rodr\u00edguez U.G.","orcid":null},"institutions":[{"id":"https://openalex.org/I147280213","display_name":"Universidad Veracruzana","ror":"https://ror.org/03efxn362","country_code":"MX","type":"education","lineage":["https://openalex.org/I147280213"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Zapata-Rodr\u00edguez U.G.","raw_affiliation_strings":["Universidad Veracruzana,Faculty of Mechanical and Naval Sciences Engineering,M&#x00E9;xico,Veracruz"],"affiliations":[{"raw_affiliation_string":"Universidad Veracruzana,Faculty of Mechanical and Naval Sciences Engineering,M&#x00E9;xico,Veracruz","institution_ids":["https://openalex.org/I147280213"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5068442493","display_name":"G. M.Cristina MacSwiney","orcid":null},"institutions":[{"id":"https://openalex.org/I147280213","display_name":"Universidad Veracruzana","ror":"https://ror.org/03efxn362","country_code":"MX","type":"education","lineage":["https://openalex.org/I147280213"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Mendoza-Barron G.","raw_affiliation_strings":["Universidad Veracruzana,Faculty of Administration,M&#x00E9;xico"],"affiliations":[{"raw_affiliation_string":"Universidad Veracruzana,Faculty of Administration,M&#x00E9;xico","institution_ids":["https://openalex.org/I147280213"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5121761787","display_name":"Mabil-Espinosa P.","orcid":null},"institutions":[{"id":"https://openalex.org/I147280213","display_name":"Universidad Veracruzana","ror":"https://ror.org/03efxn362","country_code":"MX","type":"education","lineage":["https://openalex.org/I147280213"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Mabil-Espinosa P.","raw_affiliation_strings":["Micro and Nanotechnology Research Center, Universidad Veracruzana,Veracruz,M&#x00E9;xico"],"affiliations":[{"raw_affiliation_string":"Micro and Nanotechnology Research Center, Universidad Veracruzana,Veracruz,M&#x00E9;xico","institution_ids":["https://openalex.org/I147280213"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5121776287","display_name":"Caldelas-Gonz\u00e1lez E.I.","orcid":null},"institutions":[{"id":"https://openalex.org/I147280213","display_name":"Universidad Veracruzana","ror":"https://ror.org/03efxn362","country_code":"MX","type":"education","lineage":["https://openalex.org/I147280213"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Caldelas-Gonz\u00e1lez E.I.","raw_affiliation_strings":["Universidad Veracruzana,Faculty of Mechanical and Naval Sciences Engineering,M&#x00E9;xico,Veracruz"],"affiliations":[{"raw_affiliation_string":"Universidad Veracruzana,Faculty of Mechanical and Naval Sciences Engineering,M&#x00E9;xico,Veracruz","institution_ids":["https://openalex.org/I147280213"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5121802691","display_name":"Mart\u00ednez-Castillo J.","orcid":null},"institutions":[{"id":"https://openalex.org/I147280213","display_name":"Universidad Veracruzana","ror":"https://ror.org/03efxn362","country_code":"MX","type":"education","lineage":["https://openalex.org/I147280213"]}],"countries":["MX"],"is_corresponding":false,"raw_author_name":"Mart\u00ednez-Castillo J.","raw_affiliation_strings":["Micro and Nanotechnology Research Center, Universidad Veracruzana,Veracruz,M&#x00E9;xico"],"affiliations":[{"raw_affiliation_string":"Micro and Nanotechnology Research Center, Universidad Veracruzana,Veracruz,M&#x00E9;xico","institution_ids":["https://openalex.org/I147280213"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":7,"corresponding_author_ids":["https://openalex.org/A5121788752"],"corresponding_institution_ids":["https://openalex.org/I147280213"],"apc_list":null,"apc_paid":null,"fwci":0.0,"has_fulltext":false,"cited_by_count":0,"citation_normalized_percentile":{"value":0.6987757,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":null,"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"5"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9448999762535095,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11181","display_name":"Advanced Data Storage Technologies","score":0.9448999762535095,"subfield":{"id":"https://openalex.org/subfields/1705","display_name":"Computer Networks and Communications"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10472","display_name":"Semiconductor materials and devices","score":0.0044999998062849045,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12941","display_name":"Embedded Systems and FPGA Design","score":0.0044999998062849045,"subfield":{"id":"https://openalex.org/subfields/2207","display_name":"Control and Systems Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/vhdl","display_name":"VHDL","score":0.6186000108718872},{"id":"https://openalex.org/keywords/flash-memory-emulator","display_name":"Flash memory emulator","score":0.5321000218391418},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.5212000012397766},{"id":"https://openalex.org/keywords/flash-file-system","display_name":"Flash file system","score":0.45419999957084656},{"id":"https://openalex.org/keywords/semiconductor-memory","display_name":"Semiconductor memory","score":0.43389999866485596},{"id":"https://openalex.org/keywords/nand-gate","display_name":"NAND gate","score":0.4309000074863434},{"id":"https://openalex.org/keywords/flash","display_name":"Flash (photography)","score":0.4059000015258789},{"id":"https://openalex.org/keywords/flash-memory","display_name":"Flash memory","score":0.39559999108314514}],"concepts":[{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7871000170707703},{"id":"https://openalex.org/C36941000","wikidata":"https://www.wikidata.org/wiki/Q209455","display_name":"VHDL","level":3,"score":0.6186000108718872},{"id":"https://openalex.org/C9390403","wikidata":"https://www.wikidata.org/wiki/Q3966","display_name":"Computer hardware","level":1,"score":0.5684000253677368},{"id":"https://openalex.org/C96535780","wikidata":"https://www.wikidata.org/wiki/Q5457561","display_name":"Flash memory emulator","level":5,"score":0.5321000218391418},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.5212000012397766},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49399998784065247},{"id":"https://openalex.org/C27670709","wikidata":"https://www.wikidata.org/wiki/Q5457555","display_name":"Flash file system","level":4,"score":0.45419999957084656},{"id":"https://openalex.org/C98986596","wikidata":"https://www.wikidata.org/wiki/Q1143031","display_name":"Semiconductor memory","level":2,"score":0.43389999866485596},{"id":"https://openalex.org/C124296912","wikidata":"https://www.wikidata.org/wiki/Q575178","display_name":"NAND gate","level":3,"score":0.4309000074863434},{"id":"https://openalex.org/C2777526259","wikidata":"https://www.wikidata.org/wiki/Q221836","display_name":"Flash (photography)","level":2,"score":0.4059000015258789},{"id":"https://openalex.org/C2776531357","wikidata":"https://www.wikidata.org/wiki/Q174077","display_name":"Flash memory","level":2,"score":0.39559999108314514},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.35989999771118164},{"id":"https://openalex.org/C92855701","wikidata":"https://www.wikidata.org/wiki/Q5830907","display_name":"Computer memory","level":3,"score":0.3440999984741211},{"id":"https://openalex.org/C177950962","wikidata":"https://www.wikidata.org/wiki/Q10997658","display_name":"Non-volatile memory","level":2,"score":0.3303999900817871},{"id":"https://openalex.org/C2779602883","wikidata":"https://www.wikidata.org/wiki/Q15544750","display_name":"Memory architecture","level":2,"score":0.3294000029563904},{"id":"https://openalex.org/C194739806","wikidata":"https://www.wikidata.org/wiki/Q66221","display_name":"Computer data storage","level":2,"score":0.3091999888420105},{"id":"https://openalex.org/C2777210771","wikidata":"https://www.wikidata.org/wiki/Q4927124","display_name":"Block (permutation group theory)","level":2,"score":0.3043999969959259},{"id":"https://openalex.org/C63511323","wikidata":"https://www.wikidata.org/wiki/Q908936","display_name":"Interleaved memory","level":4,"score":0.2962000072002411},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.2896000146865845},{"id":"https://openalex.org/C153247305","wikidata":"https://www.wikidata.org/wiki/Q835713","display_name":"Memory address","level":3,"score":0.2797999978065491},{"id":"https://openalex.org/C74426580","wikidata":"https://www.wikidata.org/wiki/Q719484","display_name":"Memory map","level":3,"score":0.26669999957084656},{"id":"https://openalex.org/C34172316","wikidata":"https://www.wikidata.org/wiki/Q499024","display_name":"Non-volatile random-access memory","level":5,"score":0.25600001215934753}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/enc68268.2025.11311720","is_oa":false,"landing_page_url":"https://doi.org/10.1109/enc68268.2025.11311720","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2025 Mexican International Conference on Computer Science (ENC)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.7560106515884399,"display_name":"Quality Education","id":"https://metadata.un.org/sdg/4"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":6,"referenced_works":["https://openalex.org/W1572399105","https://openalex.org/W2088805307","https://openalex.org/W2111865441","https://openalex.org/W2171888576","https://openalex.org/W2440703972","https://openalex.org/W4389392026"],"related_works":[],"abstract_inverted_index":{"The":[0,69,99],"flash":[1,39,53,134],"memory":[2,40,135,142,164,179],"has":[3],"become":[4],"over":[5],"time":[6],"a":[7,36,91,104,138,152,167,181,214],"fundamental":[8],"component":[9],"in":[10,44,184,204],"modern":[11],"digital":[12],"systems":[13],"due":[14],"to":[15,103,162,212],"its":[16],"nonvolatile":[17],"nature,":[18],"high":[19,24],"speed":[20],"writing":[21],"capabilities":[22],"and":[23,33,59,62,67,75,83,96,113,145,159,176,187],"data":[25,92,114,173,197],"store":[26],"density.":[27],"This":[28,49,191,207],"paper":[29],"presents":[30],"the":[31,120,123,125,129,195,200],"design":[32,109],"simulation":[34,70,192],"of":[35,78,132],"NAND":[37,133],"type":[38],"model":[41,50,126],"using":[42],"VHDL":[43,147],"XILINX":[45],"ISE":[46],"VIVADO":[47],"environment.":[48],"implements":[51],"main":[52],"operations:":[54],"read,":[55,73],"write":[56,74],"or":[57],"program,":[58],"block":[60],"erase":[61,76],"is":[63],"validated":[64],"both":[65],"functionally":[66],"quantitatively.":[68],"results":[71,193],"show":[72],"latencies":[77],"45-55":[79],"ns,":[80,82],"180-220":[81],"<tex":[84],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[85],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">$1.5-2":[86],"\\mu":[87],"\\mathrm{s}$</tex>":[88],"respectively,":[89],"achieving":[90],"throughput":[93],"between":[94],"8":[95],"12":[97],"MB/s.":[98],"architecture":[100],"was":[101,154,174],"simplified":[102],"1":[105],"KB":[106],"single":[107],"page":[108],"with":[110],"separate":[111],"address":[112],"lines":[115],"for":[116,119,140,202],"improved":[117],"clarity":[118],"study.":[121],"Despite":[122],"restrictions,":[124],"successfully":[127],"replicates":[128],"essential":[130],"behavior":[131],"serves":[136],"as":[137],"tool":[139],"understanding":[141],"architecture,":[143],"logic":[144],"hierarchical":[146],"design.":[148,216],"To":[149],"test":[150],"functionality":[151],"testbench":[153],"developed,":[155],"generating":[156],"clock":[157],"signals":[158],"applying":[160],"stimulus":[161],"simulate":[163],"access.":[165],"As":[166],"practical":[168],"application":[169],"sample":[170],"ECG":[171],"(electrocardiogram)":[172],"stored":[175],"retrieved":[177],"from":[178],"demonstrating":[180],"potential":[182],"use":[183],"biomedical":[185],"signal":[186],"embedded":[188],"healthcare":[189],"systems.":[190,206],"confirm":[194],"correct":[196],"storage,":[198],"ensuring":[199],"reliability":[201],"implementation":[203],"FPGA":[205],"work":[208],"could":[209],"be":[210],"implemented":[211],"develop":[213],"layout":[215]},"counts_by_year":[],"updated_date":"2026-01-03T23:08:47.215875","created_date":"2026-01-02T00:00:00"}
