{"id":"https://openalex.org/W2126179789","doi":"https://doi.org/10.1109/emeit.2011.6023114","title":"High performance Complementary Pass transistor Logic full adder","display_name":"High performance Complementary Pass transistor Logic full adder","publication_year":2011,"publication_date":"2011-08-01","ids":{"openalex":"https://openalex.org/W2126179789","doi":"https://doi.org/10.1109/emeit.2011.6023114","mag":"2126179789"},"language":"en","primary_location":{"id":"doi:10.1109/emeit.2011.6023114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/emeit.2011.6023114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2011 International Conference on Electronic & Mechanical Engineering and Information Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5019000951","display_name":"Lixin Gao","orcid":"https://orcid.org/0009-0000-8951-091X"},"institutions":[],"countries":[],"is_corresponding":true,"raw_author_name":"Lixin Gao","raw_affiliation_strings":["School of Information Engineering, Guangdong Jidian Polytechnic, Guangzhou, China","School of Information Engineering, Guangdong Jidian Polytechnic, Guangzhou 510515, China"],"affiliations":[{"raw_affiliation_string":"School of Information Engineering, Guangdong Jidian Polytechnic, Guangzhou, China","institution_ids":[]},{"raw_affiliation_string":"School of Information Engineering, Guangdong Jidian Polytechnic, Guangzhou 510515, China","institution_ids":[]}]}],"institutions":[],"countries_distinct_count":0,"institutions_distinct_count":1,"corresponding_author_ids":["https://openalex.org/A5019000951"],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":1.0599,"has_fulltext":false,"cited_by_count":11,"citation_normalized_percentile":{"value":0.80376697,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":97},"biblio":{"volume":null,"issue":null,"first_page":"4306","last_page":"4309"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9994000196456909,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T13182","display_name":"Quantum-Dot Cellular Automata","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/adder","display_name":"Adder","score":0.8535631895065308},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.7274404764175415},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6787107586860657},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.6405667066574097},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6172168254852295},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.6074516773223877},{"id":"https://openalex.org/keywords/logic-family","display_name":"Logic family","score":0.5520232915878296},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.521222710609436},{"id":"https://openalex.org/keywords/dissipation","display_name":"Dissipation","score":0.5100763440132141},{"id":"https://openalex.org/keywords/multiplexer","display_name":"Multiplexer","score":0.5095748901367188},{"id":"https://openalex.org/keywords/adiabatic-circuit","display_name":"Adiabatic circuit","score":0.505362331867218},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.5044611692428589},{"id":"https://openalex.org/keywords/integrated-injection-logic","display_name":"Integrated injection logic","score":0.503800094127655},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.4970281422138214},{"id":"https://openalex.org/keywords/logic-synthesis","display_name":"Logic synthesis","score":0.43907761573791504},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.34638625383377075},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.2548618018627167},{"id":"https://openalex.org/keywords/multiplexing","display_name":"Multiplexing","score":0.11549711227416992},{"id":"https://openalex.org/keywords/physics","display_name":"Physics","score":0.08742880821228027},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.08119803667068481}],"concepts":[{"id":"https://openalex.org/C164620267","wikidata":"https://www.wikidata.org/wiki/Q376953","display_name":"Adder","level":3,"score":0.8535631895065308},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.7274404764175415},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6787107586860657},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.6405667066574097},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6172168254852295},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.6074516773223877},{"id":"https://openalex.org/C162454741","wikidata":"https://www.wikidata.org/wiki/Q173359","display_name":"Logic family","level":4,"score":0.5520232915878296},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.521222710609436},{"id":"https://openalex.org/C135402231","wikidata":"https://www.wikidata.org/wiki/Q898440","display_name":"Dissipation","level":2,"score":0.5100763440132141},{"id":"https://openalex.org/C70970002","wikidata":"https://www.wikidata.org/wiki/Q189434","display_name":"Multiplexer","level":3,"score":0.5095748901367188},{"id":"https://openalex.org/C87606752","wikidata":"https://www.wikidata.org/wiki/Q4682637","display_name":"Adiabatic circuit","level":5,"score":0.505362331867218},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.5044611692428589},{"id":"https://openalex.org/C159903706","wikidata":"https://www.wikidata.org/wiki/Q173574","display_name":"Integrated injection logic","level":5,"score":0.503800094127655},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.4970281422138214},{"id":"https://openalex.org/C157922185","wikidata":"https://www.wikidata.org/wiki/Q173198","display_name":"Logic synthesis","level":3,"score":0.43907761573791504},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.34638625383377075},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.2548618018627167},{"id":"https://openalex.org/C19275194","wikidata":"https://www.wikidata.org/wiki/Q222903","display_name":"Multiplexing","level":2,"score":0.11549711227416992},{"id":"https://openalex.org/C121332964","wikidata":"https://www.wikidata.org/wiki/Q413","display_name":"Physics","level":0,"score":0.08742880821228027},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.08119803667068481},{"id":"https://openalex.org/C97355855","wikidata":"https://www.wikidata.org/wiki/Q11473","display_name":"Thermodynamics","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/emeit.2011.6023114","is_oa":false,"landing_page_url":"https://doi.org/10.1109/emeit.2011.6023114","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings of 2011 International Conference on Electronic & Mechanical Engineering and Information Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.6899999976158142,"id":"https://metadata.un.org/sdg/7","display_name":"Affordable and clean energy"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":5,"referenced_works":["https://openalex.org/W1518236483","https://openalex.org/W2135955108","https://openalex.org/W2141849037","https://openalex.org/W2361747216","https://openalex.org/W2371595004"],"related_works":["https://openalex.org/W2775708798","https://openalex.org/W2149316215","https://openalex.org/W2037102145","https://openalex.org/W2067192709","https://openalex.org/W2169401600","https://openalex.org/W1595196594","https://openalex.org/W2138046274","https://openalex.org/W2094083011","https://openalex.org/W1643678676","https://openalex.org/W3150018089","https://openalex.org/W1983631808","https://openalex.org/W1571873402","https://openalex.org/W1989279388","https://openalex.org/W1985184409","https://openalex.org/W2001868452","https://openalex.org/W2403642069","https://openalex.org/W2899979858","https://openalex.org/W2018884464","https://openalex.org/W2058853892","https://openalex.org/W1598025287"],"abstract_inverted_index":{"Complementary":[0],"Pass":[1],"transistor":[2],"Logic":[3],"(CPL)":[4],"is":[5],"becoming":[6],"increasingly":[7],"important":[8],"in":[9,72],"the":[10,22,51,73,79],"design":[11,75],"of":[12,16,53],"a":[13,65],"specific":[14],"class":[15],"digital":[17],"integrated":[18],"circuits":[19,35],"which":[20],"employ":[21],"XOR":[23],"and":[24,38,46,49,61,68],"MUX":[25],"operations.":[26],"In":[27],"this":[28],"paper,":[29],"we":[30],"have":[31],"designed":[32],"full":[33,55],"adder":[34,56],"using":[36],"CPL":[37,74],"CMOS":[39,81],"logic":[40,82],"respectively.":[41],"We":[42],"analyze":[43],"their":[44],"delay":[45,67],"power":[47,70],"dissipation,":[48],"run":[50],"simulations":[52,62],"two":[54],"circuits.":[57],"The":[58],"theoretical":[59],"analysis":[60],"show":[63],"that":[64],"worst-case":[66],"total":[69],"dissipation":[71],"are":[76],"better":[77],"than":[78],"conventional":[80],"design.":[83]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2024,"cited_by_count":3},{"year":2023,"cited_by_count":1},{"year":2021,"cited_by_count":1},{"year":2016,"cited_by_count":1},{"year":2014,"cited_by_count":2},{"year":2013,"cited_by_count":2}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}