{"id":"https://openalex.org/W2545825961","doi":"https://doi.org/10.1109/emccompo.2013.6735178","title":"Noise-immune design of Schmitt trigger logic gate using DTMOS for sub-threshold circuits","display_name":"Noise-immune design of Schmitt trigger logic gate using DTMOS for sub-threshold circuits","publication_year":2013,"publication_date":"2013-12-01","ids":{"openalex":"https://openalex.org/W2545825961","doi":"https://doi.org/10.1109/emccompo.2013.6735178","mag":"2545825961"},"language":"en","primary_location":{"id":"doi:10.1109/emccompo.2013.6735178","is_oa":false,"landing_page_url":"https://doi.org/10.1109/emccompo.2013.6735178","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5110947048","display_name":"Kyung-Soo Kim","orcid":null},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":true,"raw_author_name":"KyungSoo Kim","raw_affiliation_strings":["Department of Semiconductor Display Engineering, SungKyunKwan University, Suwon, KOREA"],"affiliations":[{"raw_affiliation_string":"Department of Semiconductor Display Engineering, SungKyunKwan University, Suwon, KOREA","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5043410043","display_name":"Wansoo Nah","orcid":"https://orcid.org/0000-0002-0315-3294"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"Wansoo Nah","raw_affiliation_strings":["Department of Semiconductor Display Engineering, SungKyunKwan University, Suwon, KOREA"],"affiliations":[{"raw_affiliation_string":"Department of Semiconductor Display Engineering, SungKyunKwan University, Suwon, KOREA","institution_ids":["https://openalex.org/I848706"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5100373077","display_name":"SoYoung Kim","orcid":"https://orcid.org/0000-0001-8901-3649"},"institutions":[{"id":"https://openalex.org/I848706","display_name":"Sungkyunkwan University","ror":"https://ror.org/04q78tk20","country_code":"KR","type":"education","lineage":["https://openalex.org/I848706"]}],"countries":["KR"],"is_corresponding":false,"raw_author_name":"SoYoung Kim","raw_affiliation_strings":["Department of Semiconductor Display Engineering, SungKyunKwan University, Suwon, KOREA"],"affiliations":[{"raw_affiliation_string":"Department of Semiconductor Display Engineering, SungKyunKwan University, Suwon, KOREA","institution_ids":["https://openalex.org/I848706"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5110947048"],"corresponding_institution_ids":["https://openalex.org/I848706"],"apc_list":null,"apc_paid":null,"fwci":0.7094,"has_fulltext":false,"cited_by_count":7,"citation_normalized_percentile":{"value":0.76666511,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":89,"max":96},"biblio":{"volume":null,"issue":null,"first_page":"83","last_page":"88"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10363","display_name":"Low-power high-performance VLSI design","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10323","display_name":"Analog and Mixed-Signal Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2204","display_name":"Biomedical Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10558","display_name":"Advancements in Semiconductor Devices and Circuit Design","score":0.9998000264167786,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/schmitt-trigger","display_name":"Schmitt trigger","score":0.964134693145752},{"id":"https://openalex.org/keywords/logic-gate","display_name":"Logic gate","score":0.685214102268219},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.6491376161575317},{"id":"https://openalex.org/keywords/threshold-voltage","display_name":"Threshold voltage","score":0.6436524391174316},{"id":"https://openalex.org/keywords/noise-immunity","display_name":"Noise immunity","score":0.5825274586677551},{"id":"https://openalex.org/keywords/noise","display_name":"Noise (video)","score":0.5741856098175049},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5409247875213623},{"id":"https://openalex.org/keywords/pass-transistor-logic","display_name":"Pass transistor logic","score":0.5340007543563843},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.5031866431236267},{"id":"https://openalex.org/keywords/digital-electronics","display_name":"Digital electronics","score":0.5026719570159912},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.49837303161621094},{"id":"https://openalex.org/keywords/logic-level","display_name":"Logic level","score":0.4650145173072815},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.4552816152572632},{"id":"https://openalex.org/keywords/noise-margin","display_name":"Noise margin","score":0.4289831221103668},{"id":"https://openalex.org/keywords/voltage","display_name":"Voltage","score":0.3814857602119446},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.29685544967651367},{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.165929913520813},{"id":"https://openalex.org/keywords/artificial-intelligence","display_name":"Artificial intelligence","score":0.11647900938987732}],"concepts":[{"id":"https://openalex.org/C90201813","wikidata":"https://www.wikidata.org/wiki/Q202957","display_name":"Schmitt trigger","level":3,"score":0.964134693145752},{"id":"https://openalex.org/C131017901","wikidata":"https://www.wikidata.org/wiki/Q170451","display_name":"Logic gate","level":2,"score":0.685214102268219},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.6491376161575317},{"id":"https://openalex.org/C195370968","wikidata":"https://www.wikidata.org/wiki/Q1754002","display_name":"Threshold voltage","level":4,"score":0.6436524391174316},{"id":"https://openalex.org/C2988494973","wikidata":"https://www.wikidata.org/wiki/Q179448","display_name":"Noise immunity","level":3,"score":0.5825274586677551},{"id":"https://openalex.org/C99498987","wikidata":"https://www.wikidata.org/wiki/Q2210247","display_name":"Noise (video)","level":3,"score":0.5741856098175049},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5409247875213623},{"id":"https://openalex.org/C198521697","wikidata":"https://www.wikidata.org/wiki/Q7142438","display_name":"Pass transistor logic","level":4,"score":0.5340007543563843},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.5031866431236267},{"id":"https://openalex.org/C81843906","wikidata":"https://www.wikidata.org/wiki/Q173156","display_name":"Digital electronics","level":3,"score":0.5026719570159912},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.49837303161621094},{"id":"https://openalex.org/C146569638","wikidata":"https://www.wikidata.org/wiki/Q173378","display_name":"Logic level","level":3,"score":0.4650145173072815},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.4552816152572632},{"id":"https://openalex.org/C179499742","wikidata":"https://www.wikidata.org/wiki/Q1324892","display_name":"Noise margin","level":4,"score":0.4289831221103668},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.3814857602119446},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.29685544967651367},{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.165929913520813},{"id":"https://openalex.org/C154945302","wikidata":"https://www.wikidata.org/wiki/Q11660","display_name":"Artificial intelligence","level":1,"score":0.11647900938987732},{"id":"https://openalex.org/C115961682","wikidata":"https://www.wikidata.org/wiki/Q860623","display_name":"Image (mathematics)","level":2,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/emccompo.2013.6735178","is_oa":false,"landing_page_url":"https://doi.org/10.1109/emccompo.2013.6735178","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2013 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits (EMC Compo)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"score":0.8799999952316284,"display_name":"Affordable and clean energy","id":"https://metadata.un.org/sdg/7"}],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":10,"referenced_works":["https://openalex.org/W1966367624","https://openalex.org/W1988502478","https://openalex.org/W2014337083","https://openalex.org/W2023329236","https://openalex.org/W2114830689","https://openalex.org/W2143251546","https://openalex.org/W2170636317","https://openalex.org/W2170949280","https://openalex.org/W2543097326","https://openalex.org/W4250370067"],"related_works":["https://openalex.org/W2790173003","https://openalex.org/W2974558493","https://openalex.org/W2556983729","https://openalex.org/W4293869128","https://openalex.org/W2087864384","https://openalex.org/W1864365575","https://openalex.org/W4382541827","https://openalex.org/W2114346412","https://openalex.org/W4388893688","https://openalex.org/W2218070245"],"abstract_inverted_index":{"This":[0],"paper":[1],"presents":[2],"several":[3],"Schmitt":[4,67],"trigger":[5],"logic":[6,23,52],"gates":[7,24,53],"with":[8,54,65,86],"enhanced":[9],"noise":[10,49,79],"immunity":[11,50],"using":[12,30],"variable":[13],"threshold":[14,32],"voltage":[15,19,33],"technique":[16],"for":[17,36],"sub-threshold":[18],"operation.":[20],"The":[21,77],"proposed":[22,78],"are":[25],"based":[26],"on":[27],"buffer":[28],"design":[29,82],"dynamic":[31],"MOS":[34],"(DTMOS)":[35],"low":[37],"power":[38,58],"operation":[39],"(V":[40],"<sub":[41],"xmlns:mml=\"http://www.w3.org/1998/Math/MathML\"":[42],"xmlns:xlink=\"http://www.w3.org/1999/xlink\">DD</sub>":[43],"=0.4V).":[44],"Our":[45],"solution":[46],"dramatically":[47],"improves":[48],"of":[51,72],"much":[55],"less":[56],"switching":[57],"consumption":[59],"and":[60],"significant":[61],"area":[62],"reduction":[63],"compared":[64],"CMOS":[66],"triggers":[68],"at":[69],"the":[70],"expense":[71],"slight":[73],"increase":[74],"in":[75],"delay.":[76],"immune":[80],"gate":[81],"scheme":[83],"is":[84],"verified":[85],"an":[87],"example":[88],"digital":[89],"circuit.":[90]},"counts_by_year":[{"year":2025,"cited_by_count":2},{"year":2022,"cited_by_count":1},{"year":2020,"cited_by_count":1},{"year":2016,"cited_by_count":2},{"year":2015,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}
