{"id":"https://openalex.org/W2518640795","doi":"https://doi.org/10.1109/eit.2016.7535235","title":"Implementation of elementary functions for FPGA compute accelerators","display_name":"Implementation of elementary functions for FPGA compute accelerators","publication_year":2016,"publication_date":"2016-05-01","ids":{"openalex":"https://openalex.org/W2518640795","doi":"https://doi.org/10.1109/eit.2016.7535235","mag":"2518640795"},"language":"en","primary_location":{"id":"doi:10.1109/eit.2016.7535235","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eit.2016.7535235","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Electro Information Technology (EIT)","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5021015655","display_name":"Spenser Gilliland","orcid":null},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":true,"raw_author_name":"Spenser Gilliland","raw_affiliation_strings":["Illinois Institute of Technology, Chicago, Illinois"],"affiliations":[{"raw_affiliation_string":"Illinois Institute of Technology, Chicago, Illinois","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5018536803","display_name":"Jafar Saniie","orcid":"https://orcid.org/0000-0002-2655-6950"},"institutions":[{"id":"https://openalex.org/I180949307","display_name":"Illinois Institute of Technology","ror":"https://ror.org/037t3ry66","country_code":"US","type":"education","lineage":["https://openalex.org/I180949307"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Jafar Saniie","raw_affiliation_strings":["Illinois Institute of Technology, Chicago, Illinois"],"affiliations":[{"raw_affiliation_string":"Illinois Institute of Technology, Chicago, Illinois","institution_ids":["https://openalex.org/I180949307"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5089528766","display_name":"Fernando Martinez Vallina","orcid":null},"institutions":[{"id":"https://openalex.org/I32923980","display_name":"Xilinx (United States)","ror":"https://ror.org/01rb7bk56","country_code":"US","type":"company","lineage":["https://openalex.org/I32923980"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Fernando Martinez Vallina","raw_affiliation_strings":["Xilinx, Inc., San Jose, California"],"affiliations":[{"raw_affiliation_string":"Xilinx, Inc., San Jose, California","institution_ids":["https://openalex.org/I32923980"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":["https://openalex.org/A5021015655"],"corresponding_institution_ids":["https://openalex.org/I180949307"],"apc_list":null,"apc_paid":null,"fwci":0.3153,"has_fulltext":false,"cited_by_count":2,"citation_normalized_percentile":{"value":0.57795749,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":95},"biblio":{"volume":null,"issue":null,"first_page":"0179","last_page":"0182"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T10054","display_name":"Parallel Computing and Optimization Techniques","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11697","display_name":"Numerical Methods and Algorithms","score":0.9993000030517578,"subfield":{"id":"https://openalex.org/subfields/1703","display_name":"Computational Theory and Mathematics"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10904","display_name":"Embedded Systems Design Techniques","score":0.9991000294685364,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8527716398239136},{"id":"https://openalex.org/keywords/benchmarking","display_name":"Benchmarking","score":0.7812321782112122},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.7526673078536987},{"id":"https://openalex.org/keywords/benchmark","display_name":"Benchmark (surveying)","score":0.6642857789993286},{"id":"https://openalex.org/keywords/standardization","display_name":"Standardization","score":0.6086254119873047},{"id":"https://openalex.org/keywords/implementation","display_name":"Implementation","score":0.5520945191383362},{"id":"https://openalex.org/keywords/cordic","display_name":"CORDIC","score":0.5486066341400146},{"id":"https://openalex.org/keywords/elementary-function","display_name":"Elementary function","score":0.4882235825061798},{"id":"https://openalex.org/keywords/computer-architecture","display_name":"Computer architecture","score":0.47525522112846375},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.3970262110233307},{"id":"https://openalex.org/keywords/computer-engineering","display_name":"Computer engineering","score":0.3462815582752228},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.3258950710296631},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.3213624656200409},{"id":"https://openalex.org/keywords/software-engineering","display_name":"Software engineering","score":0.16480082273483276},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.122142493724823},{"id":"https://openalex.org/keywords/operating-system","display_name":"Operating system","score":0.11186826229095459}],"concepts":[{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8527716398239136},{"id":"https://openalex.org/C86251818","wikidata":"https://www.wikidata.org/wiki/Q816754","display_name":"Benchmarking","level":2,"score":0.7812321782112122},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.7526673078536987},{"id":"https://openalex.org/C185798385","wikidata":"https://www.wikidata.org/wiki/Q1161707","display_name":"Benchmark (surveying)","level":2,"score":0.6642857789993286},{"id":"https://openalex.org/C188087704","wikidata":"https://www.wikidata.org/wiki/Q369577","display_name":"Standardization","level":2,"score":0.6086254119873047},{"id":"https://openalex.org/C26713055","wikidata":"https://www.wikidata.org/wiki/Q245962","display_name":"Implementation","level":2,"score":0.5520945191383362},{"id":"https://openalex.org/C58870171","wikidata":"https://www.wikidata.org/wiki/Q116076","display_name":"CORDIC","level":3,"score":0.5486066341400146},{"id":"https://openalex.org/C182408441","wikidata":"https://www.wikidata.org/wiki/Q824282","display_name":"Elementary function","level":2,"score":0.4882235825061798},{"id":"https://openalex.org/C118524514","wikidata":"https://www.wikidata.org/wiki/Q173212","display_name":"Computer architecture","level":1,"score":0.47525522112846375},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.3970262110233307},{"id":"https://openalex.org/C113775141","wikidata":"https://www.wikidata.org/wiki/Q428691","display_name":"Computer engineering","level":1,"score":0.3462815582752228},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.3258950710296631},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.3213624656200409},{"id":"https://openalex.org/C115903868","wikidata":"https://www.wikidata.org/wiki/Q80993","display_name":"Software engineering","level":1,"score":0.16480082273483276},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.122142493724823},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.11186826229095459},{"id":"https://openalex.org/C134306372","wikidata":"https://www.wikidata.org/wiki/Q7754","display_name":"Mathematical analysis","level":1,"score":0.0},{"id":"https://openalex.org/C205649164","wikidata":"https://www.wikidata.org/wiki/Q1071","display_name":"Geography","level":0,"score":0.0},{"id":"https://openalex.org/C162853370","wikidata":"https://www.wikidata.org/wiki/Q39809","display_name":"Marketing","level":1,"score":0.0},{"id":"https://openalex.org/C144133560","wikidata":"https://www.wikidata.org/wiki/Q4830453","display_name":"Business","level":0,"score":0.0},{"id":"https://openalex.org/C13280743","wikidata":"https://www.wikidata.org/wiki/Q131089","display_name":"Geodesy","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eit.2016.7535235","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eit.2016.7535235","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2016 IEEE International Conference on Electro Information Technology (EIT)","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[{"id":"https://metadata.un.org/sdg/8","score":0.4000000059604645,"display_name":"Decent work and economic growth"}],"awards":[],"funders":[],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":18,"referenced_works":["https://openalex.org/W1511869281","https://openalex.org/W1584008964","https://openalex.org/W1976822747","https://openalex.org/W1985956780","https://openalex.org/W2044829853","https://openalex.org/W2078249954","https://openalex.org/W2080500070","https://openalex.org/W2095230296","https://openalex.org/W2115452265","https://openalex.org/W2117568729","https://openalex.org/W2124907183","https://openalex.org/W2133156997","https://openalex.org/W2166029537","https://openalex.org/W3023573452","https://openalex.org/W4210673018","https://openalex.org/W4256629673","https://openalex.org/W6634851982","https://openalex.org/W6670099086"],"related_works":["https://openalex.org/W2000531861","https://openalex.org/W77225837","https://openalex.org/W4232963873","https://openalex.org/W2476591313","https://openalex.org/W1828585580","https://openalex.org/W2096161369","https://openalex.org/W2578777958","https://openalex.org/W2119441456","https://openalex.org/W2080500070","https://openalex.org/W2948362263"],"abstract_inverted_index":{"Field":[0],"programmable":[1],"gate":[2],"arrays":[3],"(FPGA)":[4],"are":[5],"growing":[6],"from":[7],"the":[8,14,46,54,59,64,71,74,83,91,108,113],"role":[9],"of":[10,16,48,58,73,98,107,112],"glue":[11],"logic":[12],"into":[13],"area":[15],"application":[17],"acceleration":[18],"and":[19,56,81,96,110,125],"compute.":[20],"This":[21],"is":[22],"fostered":[23],"by":[24,63],"advances":[25],"in":[26],"silicon":[27],"technologies":[28],"as":[29,31],"well":[30],"standards":[32,43],"based":[33],"methodologies":[34],"for":[35,123],"interacting":[36],"with":[37],"heterogeneous":[38,65],"compute":[39],"resources.":[40],"As":[41],"these":[42],"generally":[44],"require":[45],"implementation":[47,55,72],"elementary":[49,60],"functions,":[50,116],"this":[51,117],"work":[52],"outlines":[53,70],"evaluation":[57],"functions":[61,77],"required":[62],"programming":[66],"standard":[67],"OpenCL.":[68],"It":[69],"math":[75,115],"\u201cbuiltin\u201d":[76],"using":[78],"CORDIC":[79],"methods":[80],"details":[82],"processes":[84],"that":[85],"will":[86],"be":[87],"taken":[88],"to":[89],"benchmark":[90],"resource":[92],"usage,":[93],"maximum":[94],"frequency,":[95],"latency":[97],"each":[99],"function":[100],"on":[101],"Xilinx":[102],"7":[103],"Series":[104],"FPGAs.":[105],"Because":[106],"applicability":[109],"standardization":[111],"OpenCL":[114],"benchmarking":[118],"effort":[119],"provides":[120],"a":[121],"basis":[122],"understanding":[124],"analysing":[126],"future":[127],"implementations.":[128]},"counts_by_year":[{"year":2025,"cited_by_count":1},{"year":2017,"cited_by_count":1}],"updated_date":"2025-11-06T03:46:38.306776","created_date":"2025-10-10T00:00:00"}