{"id":"https://openalex.org/W1993169121","doi":"https://doi.org/10.1109/eit.2012.6220768","title":"Efficient AFT implementation in FPGAs to detect potential electromigration failures","display_name":"Efficient AFT implementation in FPGAs to detect potential electromigration failures","publication_year":2012,"publication_date":"2012-05-01","ids":{"openalex":"https://openalex.org/W1993169121","doi":"https://doi.org/10.1109/eit.2012.6220768","mag":"1993169121"},"language":"en","primary_location":{"id":"doi:10.1109/eit.2012.6220768","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eit.2012.6220768","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Conference on Electro/Information Technology","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5063371370","display_name":"SaiDeepa Rayaprolu","orcid":null},"institutions":[{"id":"https://openalex.org/I90871651","display_name":"University of Toledo","ror":"https://ror.org/01pbdzh19","country_code":"US","type":"education","lineage":["https://openalex.org/I90871651"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"SaiDeepa Rayaprolu","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, University of Toledo, Toledo, OH, USA","Department of Electrical Engineering and Computer Science, The University of Toledo, Toledo, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, University of Toledo, Toledo, OH, USA","institution_ids":["https://openalex.org/I90871651"]},{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, The University of Toledo, Toledo, OH, USA","institution_ids":["https://openalex.org/I90871651"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5026391476","display_name":"Srikanth Vemuru","orcid":"https://orcid.org/0000-0002-0623-9691"},"institutions":[{"id":"https://openalex.org/I150722199","display_name":"Ohio Northern University","ror":"https://ror.org/052963a64","country_code":"US","type":"education","lineage":["https://openalex.org/I150722199","https://openalex.org/I4210162304"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Srinivasa Vemuru","raw_affiliation_strings":["Department of ECE and CS, Ohio Northern University, Ada, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of ECE and CS, Ohio Northern University, Ada, OH, USA","institution_ids":["https://openalex.org/I150722199"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5014613583","display_name":"Mohammed Niamat","orcid":"https://orcid.org/0000-0002-1896-1569"},"institutions":[{"id":"https://openalex.org/I90871651","display_name":"University of Toledo","ror":"https://ror.org/01pbdzh19","country_code":"US","type":"education","lineage":["https://openalex.org/I90871651"]}],"countries":["US"],"is_corresponding":false,"raw_author_name":"Mohammed Niamat","raw_affiliation_strings":["Department of Electrical Engineering and Computer Science, University of Toledo, Toledo, OH, USA","Department of Electrical Engineering and Computer Science, The University of Toledo, Toledo, OH, USA"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, University of Toledo, Toledo, OH, USA","institution_ids":["https://openalex.org/I90871651"]},{"raw_affiliation_string":"Department of Electrical Engineering and Computer Science, The University of Toledo, Toledo, OH, USA","institution_ids":["https://openalex.org/I90871651"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":3,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":0.2929,"has_fulltext":false,"cited_by_count":1,"citation_normalized_percentile":{"value":0.54986889,"is_in_top_1_percent":false,"is_in_top_10_percent":false},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"1","last_page":"6"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11032","display_name":"VLSI and Analog Circuit Testing","score":1.0,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T14117","display_name":"Integrated Circuits and Semiconductor Failure Analysis","score":1.0,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T12122","display_name":"Physical Unclonable Functions (PUFs) and Hardware Security","score":0.9994999766349792,"subfield":{"id":"https://openalex.org/subfields/1708","display_name":"Hardware and Architecture"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/electromigration","display_name":"Electromigration","score":0.942218542098999},{"id":"https://openalex.org/keywords/field-programmable-gate-array","display_name":"Field-programmable gate array","score":0.8876749277114868},{"id":"https://openalex.org/keywords/modular-design","display_name":"Modular design","score":0.6825268268585205},{"id":"https://openalex.org/keywords/virtex","display_name":"Virtex","score":0.6548606753349304},{"id":"https://openalex.org/keywords/interconnection","display_name":"Interconnection","score":0.6494746208190918},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.6239230632781982},{"id":"https://openalex.org/keywords/embedded-system","display_name":"Embedded system","score":0.49120134115219116},{"id":"https://openalex.org/keywords/process","display_name":"Process (computing)","score":0.4461739659309387},{"id":"https://openalex.org/keywords/parallel-computing","display_name":"Parallel computing","score":0.42989209294319153},{"id":"https://openalex.org/keywords/computational-science","display_name":"Computational science","score":0.35117200016975403},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.19911935925483704},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.0933782160282135}],"concepts":[{"id":"https://openalex.org/C138055206","wikidata":"https://www.wikidata.org/wiki/Q1319010","display_name":"Electromigration","level":2,"score":0.942218542098999},{"id":"https://openalex.org/C42935608","wikidata":"https://www.wikidata.org/wiki/Q190411","display_name":"Field-programmable gate array","level":2,"score":0.8876749277114868},{"id":"https://openalex.org/C101468663","wikidata":"https://www.wikidata.org/wiki/Q1620158","display_name":"Modular design","level":2,"score":0.6825268268585205},{"id":"https://openalex.org/C2777674469","wikidata":"https://www.wikidata.org/wiki/Q20741011","display_name":"Virtex","level":3,"score":0.6548606753349304},{"id":"https://openalex.org/C123745756","wikidata":"https://www.wikidata.org/wiki/Q1665949","display_name":"Interconnection","level":2,"score":0.6494746208190918},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.6239230632781982},{"id":"https://openalex.org/C149635348","wikidata":"https://www.wikidata.org/wiki/Q193040","display_name":"Embedded system","level":1,"score":0.49120134115219116},{"id":"https://openalex.org/C98045186","wikidata":"https://www.wikidata.org/wiki/Q205663","display_name":"Process (computing)","level":2,"score":0.4461739659309387},{"id":"https://openalex.org/C173608175","wikidata":"https://www.wikidata.org/wiki/Q232661","display_name":"Parallel computing","level":1,"score":0.42989209294319153},{"id":"https://openalex.org/C459310","wikidata":"https://www.wikidata.org/wiki/Q117801","display_name":"Computational science","level":1,"score":0.35117200016975403},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.19911935925483704},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.0933782160282135},{"id":"https://openalex.org/C31258907","wikidata":"https://www.wikidata.org/wiki/Q1301371","display_name":"Computer network","level":1,"score":0.0},{"id":"https://openalex.org/C111919701","wikidata":"https://www.wikidata.org/wiki/Q9135","display_name":"Operating system","level":1,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eit.2012.6220768","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eit.2012.6220768","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"2012 IEEE International Conference on Electro/Information Technology","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[{"id":"https://openalex.org/F4320306076","display_name":"National Science Foundation","ror":"https://ror.org/021nxhr62"}],"has_content":{"grobid_xml":false,"pdf":false},"content_urls":null,"referenced_works_count":9,"referenced_works":["https://openalex.org/W1972563218","https://openalex.org/W1993169121","https://openalex.org/W2006584048","https://openalex.org/W2066902804","https://openalex.org/W2083092557","https://openalex.org/W2126506044","https://openalex.org/W2133641782","https://openalex.org/W2140897908","https://openalex.org/W2169952903"],"related_works":["https://openalex.org/W2136403807","https://openalex.org/W796810817","https://openalex.org/W2544043553","https://openalex.org/W2546284597","https://openalex.org/W2348562861","https://openalex.org/W2540393334","https://openalex.org/W1983570530","https://openalex.org/W2390042878","https://openalex.org/W2062932566","https://openalex.org/W2271847574"],"abstract_inverted_index":{"An":[0],"efficient":[1],"and":[2,39,54],"modular":[3],"architecture":[4],"is":[5,34],"used":[6,35],"to":[7,18,36],"implement":[8,37],"Arithmetic":[9],"Fourier":[10],"Transform":[11],"algorithm":[12],"as":[13],"a":[14],"Built-in-Self":[15],"Test":[16],"structure":[17],"identify":[19],"electromigration":[20,42],"faults":[21],"in":[22,29],"FPGAs.":[23],"Xilinx":[24],"Virtex":[25],"5":[26],"FPGA,":[27],"implemented":[28],"65":[30],"nm":[31],"fabrication":[32],"process,":[33],"BIST":[38],"simulate":[40],"the":[41],"failure":[43],"mechanisms.":[44],"Fault":[45],"signatures":[46],"are":[47,57],"developed":[48],"for":[49],"different":[50],"interconnect":[51],"FPGA":[52],"resources":[53],"simulation":[55],"results":[56],"presented.":[58]},"counts_by_year":[{"year":2012,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
