{"id":"https://openalex.org/W2168432482","doi":"https://doi.org/10.1109/eh.2004.1310807","title":"Evolutionary synthesis of analog circuits using only MOS transistors","display_name":"Evolutionary synthesis of analog circuits using only MOS transistors","publication_year":2004,"publication_date":"2004-11-13","ids":{"openalex":"https://openalex.org/W2168432482","doi":"https://doi.org/10.1109/eh.2004.1310807","mag":"2168432482"},"language":"en","primary_location":{"id":"doi:10.1109/eh.2004.1310807","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eh.2004.1310807","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004.","raw_type":"proceedings-article"},"type":"article","indexed_in":["crossref"],"open_access":{"is_oa":false,"oa_status":"closed","oa_url":null,"any_repository_has_fulltext":false},"authorships":[{"author_position":"first","author":{"id":"https://openalex.org/A5109183364","display_name":"P.F. Vieira","orcid":null},"institutions":[{"id":"https://openalex.org/I122140584","display_name":"Universidade Federal do Rio de Janeiro","ror":"https://ror.org/03490as77","country_code":"BR","type":"education","lineage":["https://openalex.org/I122140584"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"P.F. Vieira","raw_affiliation_strings":["LPC/PEE/COPPE/Federal University of Rio de Janeiro, Rio de Janeiro, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LPC/PEE/COPPE/Federal University of Rio de Janeiro, Rio de Janeiro, Brazil","institution_ids":["https://openalex.org/I122140584"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5028780847","display_name":"Leonardo Bruno de S\u00e1","orcid":"https://orcid.org/0000-0001-5896-6973"},"institutions":[{"id":"https://openalex.org/I122140584","display_name":"Universidade Federal do Rio de Janeiro","ror":"https://ror.org/03490as77","country_code":"BR","type":"education","lineage":["https://openalex.org/I122140584"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"L.B. Sa","raw_affiliation_strings":["LPC/PEE/COPPE/Federal University of Rio de Janeiro, Rio de Janeiro, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LPC/PEE/COPPE/Federal University of Rio de Janeiro, Rio de Janeiro, Brazil","institution_ids":["https://openalex.org/I122140584"]}]},{"author_position":"middle","author":{"id":"https://openalex.org/A5070460595","display_name":"J.P.B. Botelho","orcid":null},"institutions":[{"id":"https://openalex.org/I122140584","display_name":"Universidade Federal do Rio de Janeiro","ror":"https://ror.org/03490as77","country_code":"BR","type":"education","lineage":["https://openalex.org/I122140584"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"J.P.B. Botelho","raw_affiliation_strings":["LPC/PEE/COPPE/Federal University of Rio de Janeiro, Rio de Janeiro, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LPC/PEE/COPPE/Federal University of Rio de Janeiro, Rio de Janeiro, Brazil","institution_ids":["https://openalex.org/I122140584"]}]},{"author_position":"last","author":{"id":"https://openalex.org/A5050547628","display_name":"A. Mesquita","orcid":"https://orcid.org/0009-0007-6804-3292"},"institutions":[{"id":"https://openalex.org/I122140584","display_name":"Universidade Federal do Rio de Janeiro","ror":"https://ror.org/03490as77","country_code":"BR","type":"education","lineage":["https://openalex.org/I122140584"]}],"countries":["BR"],"is_corresponding":false,"raw_author_name":"A. Mesquita","raw_affiliation_strings":["LPC/PEE/COPPE/Federal University of Rio de Janeiro, Rio de Janeiro, Brazil"],"raw_orcid":null,"affiliations":[{"raw_affiliation_string":"LPC/PEE/COPPE/Federal University of Rio de Janeiro, Rio de Janeiro, Brazil","institution_ids":["https://openalex.org/I122140584"]}]}],"institutions":[],"countries_distinct_count":1,"institutions_distinct_count":4,"corresponding_author_ids":[],"corresponding_institution_ids":[],"apc_list":null,"apc_paid":null,"fwci":3.2383,"has_fulltext":false,"cited_by_count":13,"citation_normalized_percentile":{"value":0.92621351,"is_in_top_1_percent":false,"is_in_top_10_percent":true},"cited_by_percentile_year":{"min":90,"max":94},"biblio":{"volume":null,"issue":null,"first_page":"38","last_page":"45"},"is_retracted":false,"is_paratext":false,"is_xpac":false,"primary_topic":{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},"topics":[{"id":"https://openalex.org/T11975","display_name":"Evolutionary Algorithms and Applications","score":0.9998999834060669,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T11522","display_name":"VLSI and FPGA Design Techniques","score":0.9790999889373779,"subfield":{"id":"https://openalex.org/subfields/2208","display_name":"Electrical and Electronic Engineering"},"field":{"id":"https://openalex.org/fields/22","display_name":"Engineering"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}},{"id":"https://openalex.org/T10100","display_name":"Metaheuristic Optimization Algorithms Research","score":0.9775999784469604,"subfield":{"id":"https://openalex.org/subfields/1702","display_name":"Artificial Intelligence"},"field":{"id":"https://openalex.org/fields/17","display_name":"Computer Science"},"domain":{"id":"https://openalex.org/domains/3","display_name":"Physical Sciences"}}],"keywords":[{"id":"https://openalex.org/keywords/transistor","display_name":"Transistor","score":0.6995958089828491},{"id":"https://openalex.org/keywords/analogue-electronics","display_name":"Analogue electronics","score":0.6961746215820312},{"id":"https://openalex.org/keywords/electronic-circuit","display_name":"Electronic circuit","score":0.6241725087165833},{"id":"https://openalex.org/keywords/computer-science","display_name":"Computer science","score":0.5776896476745605},{"id":"https://openalex.org/keywords/cmos","display_name":"CMOS","score":0.5684118270874023},{"id":"https://openalex.org/keywords/coding","display_name":"Coding (social sciences)","score":0.5668405890464783},{"id":"https://openalex.org/keywords/electronic-engineering","display_name":"Electronic engineering","score":0.5114213824272156},{"id":"https://openalex.org/keywords/sizing","display_name":"Sizing","score":0.4861711859703064},{"id":"https://openalex.org/keywords/analog-multiplier","display_name":"Analog multiplier","score":0.4704873859882355},{"id":"https://openalex.org/keywords/analog-device","display_name":"Analog device","score":0.4285297393798828},{"id":"https://openalex.org/keywords/topology","display_name":"Topology (electrical circuits)","score":0.419467955827713},{"id":"https://openalex.org/keywords/engineering","display_name":"Engineering","score":0.3042628765106201},{"id":"https://openalex.org/keywords/electrical-engineering","display_name":"Electrical engineering","score":0.2584526538848877},{"id":"https://openalex.org/keywords/mathematics","display_name":"Mathematics","score":0.20586875081062317},{"id":"https://openalex.org/keywords/analog-signal","display_name":"Analog signal","score":0.2052963674068451}],"concepts":[{"id":"https://openalex.org/C172385210","wikidata":"https://www.wikidata.org/wiki/Q5339","display_name":"Transistor","level":3,"score":0.6995958089828491},{"id":"https://openalex.org/C29074008","wikidata":"https://www.wikidata.org/wiki/Q174925","display_name":"Analogue electronics","level":3,"score":0.6961746215820312},{"id":"https://openalex.org/C134146338","wikidata":"https://www.wikidata.org/wiki/Q1815901","display_name":"Electronic circuit","level":2,"score":0.6241725087165833},{"id":"https://openalex.org/C41008148","wikidata":"https://www.wikidata.org/wiki/Q21198","display_name":"Computer science","level":0,"score":0.5776896476745605},{"id":"https://openalex.org/C46362747","wikidata":"https://www.wikidata.org/wiki/Q173431","display_name":"CMOS","level":2,"score":0.5684118270874023},{"id":"https://openalex.org/C179518139","wikidata":"https://www.wikidata.org/wiki/Q5140297","display_name":"Coding (social sciences)","level":2,"score":0.5668405890464783},{"id":"https://openalex.org/C24326235","wikidata":"https://www.wikidata.org/wiki/Q126095","display_name":"Electronic engineering","level":1,"score":0.5114213824272156},{"id":"https://openalex.org/C2777767291","wikidata":"https://www.wikidata.org/wiki/Q1080291","display_name":"Sizing","level":2,"score":0.4861711859703064},{"id":"https://openalex.org/C98142538","wikidata":"https://www.wikidata.org/wiki/Q485005","display_name":"Analog multiplier","level":4,"score":0.4704873859882355},{"id":"https://openalex.org/C90711627","wikidata":"https://www.wikidata.org/wiki/Q3742408","display_name":"Analog device","level":4,"score":0.4285297393798828},{"id":"https://openalex.org/C184720557","wikidata":"https://www.wikidata.org/wiki/Q7825049","display_name":"Topology (electrical circuits)","level":2,"score":0.419467955827713},{"id":"https://openalex.org/C127413603","wikidata":"https://www.wikidata.org/wiki/Q11023","display_name":"Engineering","level":0,"score":0.3042628765106201},{"id":"https://openalex.org/C119599485","wikidata":"https://www.wikidata.org/wiki/Q43035","display_name":"Electrical engineering","level":1,"score":0.2584526538848877},{"id":"https://openalex.org/C33923547","wikidata":"https://www.wikidata.org/wiki/Q395","display_name":"Mathematics","level":0,"score":0.20586875081062317},{"id":"https://openalex.org/C13412647","wikidata":"https://www.wikidata.org/wiki/Q174948","display_name":"Analog signal","level":3,"score":0.2052963674068451},{"id":"https://openalex.org/C165801399","wikidata":"https://www.wikidata.org/wiki/Q25428","display_name":"Voltage","level":2,"score":0.0},{"id":"https://openalex.org/C105795698","wikidata":"https://www.wikidata.org/wiki/Q12483","display_name":"Statistics","level":1,"score":0.0},{"id":"https://openalex.org/C153349607","wikidata":"https://www.wikidata.org/wiki/Q36649","display_name":"Visual arts","level":1,"score":0.0},{"id":"https://openalex.org/C84462506","wikidata":"https://www.wikidata.org/wiki/Q173142","display_name":"Digital signal processing","level":2,"score":0.0},{"id":"https://openalex.org/C142362112","wikidata":"https://www.wikidata.org/wiki/Q735","display_name":"Art","level":0,"score":0.0}],"mesh":[],"locations_count":1,"locations":[{"id":"doi:10.1109/eh.2004.1310807","is_oa":false,"landing_page_url":"https://doi.org/10.1109/eh.2004.1310807","pdf_url":null,"source":null,"license":null,"license_id":null,"version":"publishedVersion","is_accepted":true,"is_published":true,"raw_source_name":"Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004.","raw_type":"proceedings-article"}],"best_oa_location":null,"sustainable_development_goals":[],"awards":[],"funders":[],"has_content":{"pdf":false,"grobid_xml":false},"content_urls":null,"referenced_works_count":7,"referenced_works":["https://openalex.org/W1537352836","https://openalex.org/W1557082763","https://openalex.org/W1608449908","https://openalex.org/W2126428215","https://openalex.org/W2132857212","https://openalex.org/W2145358696","https://openalex.org/W2158361181"],"related_works":["https://openalex.org/W2897384411","https://openalex.org/W2992641854","https://openalex.org/W2138543354","https://openalex.org/W4300714671","https://openalex.org/W2107333082","https://openalex.org/W4254962629","https://openalex.org/W2063415734","https://openalex.org/W2044182320","https://openalex.org/W1956840144","https://openalex.org/W2076485395"],"abstract_inverted_index":{"The":[0],"synthesis":[1],"of":[2,61],"analog":[3,26,51],"circuits":[4,27],"assuming":[5],"a":[6,40,62],"hypothetical":[7],"intrinsic":[8],"evolutionary":[9],"integrated":[10],"hardware":[11],"platform":[12],"containing":[13],"only":[14],"CMOS":[15],"transistors":[16,31],"is":[17,20],"examined.":[18],"It":[19],"shown":[21],"that":[22],"to":[23,46],"efficiently":[24],"synthesize":[25],"both":[28],"topology":[29],"and":[30,54],"sizing":[32,65],"should":[33],"be":[34],"treated":[35],"separately.":[36],"To":[37],"this":[38],"end":[39],"flexible":[41],"chromosome":[42],"coding":[43],"scheme":[44],"able":[45],"generate":[47],"the":[48,55,58],"most":[49],"common":[50],"building":[52],"blocks":[53],"inclusion":[56],"in":[57],"genetic":[59],"algorithm":[60],"separate":[63],"transistor":[64],"step":[66],"are":[67],"proposed.":[68]},"counts_by_year":[{"year":2016,"cited_by_count":1},{"year":2015,"cited_by_count":1},{"year":2013,"cited_by_count":1}],"updated_date":"2026-06-11T09:08:48.828518","created_date":"2025-10-10T00:00:00"}
